Verilog: error instantiating module

Question

I'm trying to write re-usable modules and have run into a problem. The code follows:

35  always @(BTN) begin  
36    case (BTN)  
37      4'b0001:  
38        begin  
39          digit1 <= digit1 + 1;  
40          sevensegcase digi1 (      // the module i'm trying to reuse  
41            .SEG_SEL_IN(n2B0[1:0],  // n2B0 is a defined constant  
42            .BIN_IN(digit1[3:0]),  
43            .DOT_IN(n1B1),          // another constant  
44            .SEG_SEL_OUT(AN[3:0]),  // Send digit selection to the anodes  
45            .HEX_OUT(A_TO_G[7:0])); // Select appropriate segments  
46         end  

......  
......  
......

When I save the module, it compiles with errors.
When I Synthesize the module I get:

ERROR:HDLCompliers:26 - "Seven_Seg.v" line 40 unexpected token 'sevensegcase'

If I place the instantiation outside the always block I get the same error.

The Brofessor · Accepted Answer · 2015-08-05 01:02:03Z

1

You are instantiating a module inside an always @ block. Instantiate it outside the always @ block, give it input wires, and in you always @ block assign those input wires to desired signals.

sevensegcase digi1 (
  .SEG_SEL_IN(n2B0[1:0], // n2B0 is a defined constant
  .BIN_IN(digit1[3:0]),
  .DOT_IN(n1B1), // another constant
  .SEG_SEL_OUT(AN[3:0]), // Send digit selection to the anodes
  .HEX_OUT(A_TO_G[7:0])); // Select appropriate segments
)

reg digit_reg[3:0];

always @(BTN) begin
  case (BTN)
    4'b0001:
    begin
      digit_reg <= digit_reg + 1;
    end

assign digit1 = digit_reg;

Side note: Don't forget your default: case!

edited Aug 5, 2015 at 1:02

answered Aug 5, 2015 at 0:54

The Brofessor

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1 Comment

Morgan Over a year ago

I would also recommend using automatic sensitivity lists always @* instead of always @(BTN).

Barry Moss · Accepted Answer · 2015-08-05 20:51:54Z

0

I think the problem is that you may be swapping your module name and instance name. When you instantiate a module in Verilog it needs to be in the format:

module_name instance_name (port_a, port_b, ...);

I'm guessing that digi1 may be your module name and sevensegcase is the instance name? If so, you've transposed the order, and if you fix this, it should compile. Also, make sure you compile your submodule before the top module.

answered Aug 5, 2015 at 20:51

Barry Moss

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