Verilog : For loop inside an always

Question

I am trying to implement a module that use a for loop inside a always block We are using an array of 0 & 1 in order to record the number of signal received during a certain time.

Unfortunatly we received that kind of error :

ERROR:Xst:2636 - "Tourniquet.v" line 54: Loop has iterated 10000 times. Use "set -loop_iteration_limit XX" to iterate more.

It seems that the for loop isn't allowed inside a always block (The n doesn't seems to reset). I have looked at various website and forum but don't have found any solutions.

Here is my code :

  module Tourniquet(
    input t0,
    input mvt,
     input clk,
    output init
    );

reg initialisation;
reg [0:99] memoire;
reg count = 0;
reg compteur = 0;
reg n;

assign init = initialisation;

always @(posedge clk) 
begin
    if (count==99) 
    begin 
            if (mvt)
            begin 
            memoire[count]=1;
            count=0;
            end

            else
            begin 
            memoire[count]=0;
            count=0;
            end
    end 

    else
    begin 
            if (mvt)
            begin 
            memoire[count]=1;
            count = count + 1;
            end

            else
            begin 
            memoire[count]=0;
            count = count + 1;
            end
    end
end

always @(posedge clk) 
begin
initialisation = 0;
for (n=0; n<99; n=n+1) compteur = compteur + memoire[n];
if (compteur>10) initialisation = 1;
compteur = 0;
end

endmodule

I can't find the solution nor be sure of what is the problem, any tips or help is welcomed. Thank you very much !

sharvil111 · Accepted Answer · 2016-04-01 16:36:36Z

5

You need the loop to iterate 100 times. For that, you need atleast 8 bit counter variable.

But here, n is declared as reg n, a single bit counter variable. So, n+1 gives 1 and doing n+1 again gives 0.

So, the condition of for loop for which n<100 is always satisfied. And the for loop never terminates.

This is the main reason your for loop iterates many many times.

Generally integer datatype is used for these kind of counters. integer is similar to 32 bit reg. Declare n as integer n or reg [7:0] n to have proper increment of counter and proper termination of loop.

edited Apr 1, 2016 at 16:36

answered Apr 1, 2016 at 16:31

sharvil111

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Matthew · Accepted Answer · 2016-04-01 17:15:39Z

4

Further to @sharvil111's answer, I see all these are single bits:

reg initialisation;
reg count = 0;
reg compteur = 0;
reg n;

An N bit reg in Verilog is normally declared, eg:

reg [N-1:0] n;

where N is some number (constant). And I see this is a 100-bit number:

reg [0:99] memoire;

Obviously, I don't know your design intent, but I suspect you wanted an array of N-bit numbers:

reg [N-1:0] memoire [0:99];

where N is again some number (constant).

answered Apr 1, 2016 at 17:15

Matthew

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