I am writing a test bench for AND module but it gives me the following error near "end": syntax error, unexpected end.
here is my code:
module TestAND();
reg A;
reg B;
wire C;
AND inst(A,B,C);
initial begin
A=1;
B=0;
#100
end
2 Answers
You need to add ;after #100 and you also missing endmodule at the end.
Comments
I see a couple things here, you have an incorrect data type: reg is only used in an always block, and so here everything should be type wire. Also if I recall correctly the primitives usually have the output first, so you would probably want AND my_and (c,a,b);
However, usually you don't use primitives directly unless you're creating libraries, and would want to use assign c = a & b; instead.
1 Comment
Greg
A
reg can be assigned in an always or initial block. A wire can be assigned by an assign statement or module/primitive instantiation. Verilog primitives have lower-case names, AND could a user defined module not being shown.
#100;, instead of#100