Why am I getting syntax error near endmodule

Question

I'm trying to write a module Inc_dec(L) that receives and number a, and two bits inc and dec and updates the sum and overflow/underflow according to the sum of a+inc+dec. In case of an overflow the sum is updated to 0, if an underflow occurs, the sum is L-1, otherwise no change.

Here is my code:

module Inc_Dec(a, inc, dec, sum, overflow, underflow);

parameter L = 10;
parameter N = $clog2(L);

input [N-1:0] a;
input inc, dec;
output reg [N-1:0] sum;
output overflow, underflow;

wire [1:0] sum_inc;
wire [N-1:0] sum_adder;
wire co;
wire ci;
reg dec_exp;
reg dec_reg;
reg of;
reg uf;

assign overflow = of;
assign underflow = uf;
//assign sum = sum_adder; 


Adder #(2) add1 ({0,inc}, {dec_exp,dec_reg}, 0, sum_inc, co);  
Adder #(N) add2 (a, { {(N-2){1'b0}},sum_inc }, 0, sum_adder, co); 

always @(*) begin
        if (dec > 0) begin
            dec_reg = 1;
            dec_exp = 1;
        end 
        else begin
            dec_reg = 0;
            dec_exp = 0;
  `         end
        if({co,sum_adder} >= L) begin
            of = 1;
            uf = 0;
            sum = 0;
        end
        else if({co,sum_adder} < 0) begin
            uf = 1;
            of = 0;
            sum = L-1;
        end
        else begin
            of = 0;
            uf = 0;
            sum = sum_adder[N-1:0];
        end
end 

endmodule

But I'm getting a syntax error near endmodule, plus some other errors I don't understand such as: Macro is not defined. can anyone help me find the problem?

Oldfart · Accepted Answer · 2019-12-28 12:19:48Z

1

The first issue is that you have quote in line 37:

  `         end
  ^ Here

The next issue which is likely to pop up is that you have a signal co which you use in:

Adder #(2) add1 ({0,inc}, {dec_exp,dec_reg}, 0, sum_inc, co);  
Adder #(N) add2 (a, { {(N-2){1'b0}},sum_inc }, 0, sum_adder, co);

I don't know the code of the Adder and I may be presumptuous but my guess is that the last port of the adder is an output. In which case you have a problem: co is used in both cases for the output thus it is assigned a value twice. Or is what is called "multiple driven". You should fix that.

There are some other issues which I noticed while looking at your code:

Please use to the new port definition format:

module Inc_Dec
#(parameter L = 10,
            N = $clog2(L)
 )
( input [N-1:0] a,
  input inc, dec,
  output reg [N-1:0] sum,
  output overflow, underflow
  );

The same holds when instancing a module:

Adder #(2) add1 (
    .portname1 ( {0,inc} ),         
    .portname2 ( {dec_exp,dec_reg} ),
    .portname3 ( 0 ),
    ...
  );

Again I don't know the code of the Adder but in one place you use: {0,inc} which does not add anything except that you may be picky about passing the right size of vector. But that is contrary to a little further where you use 0, as argument because that is a 32-bit wide value.

Default values are unsigned so this:

if({co,sum_adder} < 0)

will not work. If you would interpret {co,sum_adder} as a signed value then it is negative if the co is set. Thus you only have to check co:

if (co)

I only glanced at your code so there may be more errors, but I suggest you fix these first.

(And complements on copy-pasting the real code otherwise it would have been difficult to find the extra quote)

answered Dec 28, 2019 at 12:19

Oldfart

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2 Comments

Kuper Over a year ago

Thanks for the help. Referring to your comment: "But that is contrary to a little further where you use 0, as argument because that is a 32-bit wide value." When I use constants such as 0, the compiler automatically sets them as a 32-bit word?

Oldfart Over a year ago

Yes, any unsigned constant is 32 bit wide in Verilog.

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