Illegal sequential statement. error using std_logic_vector

Question

i have a project in VHDL and its my first time using it. i need to create an adder/substractor constructed from full adders and it need to have the ability to add between 8 to 32 bits number. i defined a generic but when trying to run the code i get Illegal sequential statement. the code is this:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all; 
entity Add_Sub is
  generic (N : integer := 8); 
  port(addsub_line: in std_logic;
        A: in std_logic_vector(N-1 downto 0);
        B: in std_logic_vector(N-1 downto 0);
        SumOut: out std_logic_vector(N-1 downto 0);
        Cout: out std_logic);
end Add_Sub;

architecture struct of Add_Sub is
  component FA_Ent is
      port(a: in std_logic;
       b: in std_logic;
       carry_in: in std_logic;
       sum: out std_logic;
       carry_out: out std_logic);
  end component;
  component XOR_GATE is
    port(A: in std_logic;
         B: in std_logic;
         F: out std_logic);
  end component;

  signal BxorAddSub: std_logic_vector(N-1 downto 0);
  begin 
    process 
      begin
      for i in 0 to N-1 loop
        BxorAddSubLine: XOR_GATE port map(B(0), addsub_line, BxorAddSub(0));
      end loop;
    end process;
  end struct;

i guess somewhere im using the loop wrong. im trying to do the xor for all the bits i have and i dont know how many how i got so i must use the loop anyone know why i get the error or how i should do what im trying to achive? thank you

A component instantiation is a concurrent statement suitable for a generate statement with a for generate scheme which can contain concurrent statements while a process statement can only contain sequential statements. — user1155120
– user1155120, Commented Apr 27, 2017 at 23:42
If it is your first project, you may not yet know, that you have to forget about almost everything that you know about programming, because this is NOT programming. Here you have real hardware logic components, not program with execution flow. — Staszek
– Staszek, Commented Apr 28, 2017 at 8:21

scary_jeff · Accepted Answer · 2017-04-28 08:40:30Z

2

Your basic issue is that you cannot instantiate a component from inside a process:

process 
begin
  for i in 0 to N-1 loop
    BxorAddSubLine: XOR_GATE port map(B(0), addsub_line, BxorAddSub(0));
  end loop;
end process;

The correct way to write this would be:

XorGates : for i in 0 to N-1 generate
  BxorAddSubLine: XOR_GATE port map(B(0), addsub_line, BxorAddSub(0));
end generate;

Note also that positional association in port maps is generally considered bad practice. Named association is more readable and less error prone:

BxorAddSubLine: XOR_GATE
  port map(A => B(0),
           B => addsub_line,
           F => BxorAddSub(0));

Lastly, all your BxorAddSubLine instances connect to B(0) and BxorAddSub(0); this is probably not what you wanted. Perhaps B(i) and BxorAddSub(i)?

edited Apr 28, 2017 at 8:40

answered Apr 28, 2017 at 7:52

scary_jeff

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1 Comment

Staszek Over a year ago

Actually, probably B(i) and BxorAddSub(i). This way you connect everything to N instead of 0.

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