how to call a function in Verilog and specify parameters to it?

Question

How can I call a function inside a module in verilog, with the function having parameters, and define the parameters to it?

For a trivial instance:

function automatic void inv();
  parameter W = 1;
  input logic [W:0] in;
  output logic [W:0] out;

  out = ~in;

endfunction

How would I call this and define W in the call?

In what context is the function called? We need a more complete example. — user597225
– user597225, Commented Aug 30, 2012 at 3:52
possible duplicate of Width independent functions (Solution Found) — Greg
– Greg, Commented Apr 14, 2014 at 21:28

toolic · Accepted Answer · 2012-08-30 20:40:00Z

1

You cannot override a parameter value when calling a function. There is no syntax for this specified in the IEEE Std (1800-2009).

edited Aug 30, 2012 at 20:40

answered Aug 30, 2012 at 20:23

toolic

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user597225 · Accepted Answer · 2012-08-31 03:48:10Z

1

As stated parameters are constant and cannot be changed after design elaboration. The dimensions are part of the data type so they also must be constant during design elaboration. If all your function calls are outside procedural contexts you might be able to get away with passing in a constant as an argument. I don't recommend doing this.

answered Aug 31, 2012 at 3:48

user597225

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