Turning a number negative in Verilog

Question

When you have a binary number, A = 5'b00100, and you get the negative version of it, B.

 reg signed [4:0] A, B;
 B = -A;

What does this do?

Marty · Accepted Answer · 2012-11-22 13:49:52Z

2

It'll create the twos complement of the number: flip the bits and add one!

https://en.wikipedia.org/wiki/Two%27s_complement

answered Nov 22, 2012 at 13:49

Marty

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user749632 · Accepted Answer · 2018-05-24 19:06:37Z

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in the above case if both A/B are declared as 'signed', then the simple logic of B = -A should work and i tried in a simple case and it works. Verilog already does everything in 2's complement.

answered May 24, 2018 at 19:06

user749632

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