Verilog specify block within for-loop

Question

I am trying to model path delays for an n-bit wide signal. I can do this fine if I explicitly define the delay for each individual bit, like this (n=3):

specify
    (in_data[0] => delayed_data[0]) = 5;
    (in_data[1] => delayed_data[1]) = 2;
    (in_data[2] => delayed_data[2]) = 1;
endspecify

However, I want to be able to specify random delays for each bit of in_data when in_data is n-bits wide. My idea was something like this:

for (n=0;n<DATA_WIDTH-1;n=n+1)
begin
    specify
       (in_data[n] => delayed_data[n]) = {$random};
    endspecify
end

This gives me an error:

near 'specify': syntax error, unexpected specify

I also tried placing the for loop within the specify block. This resulted in the following error:

near 'begin': syntax error, unexpected begin, expecting endspecify

I would really appreciate any tips on how to do this correctly.

DevGoldm · Accepted Answer · 2013-09-03 16:46:42Z

According to the Doulos Verilog Reference Guide (page 84) a specify block can only occur within module and endmodule tags, and not within anything else.

According to this Verilog reference website:

The Specify block was designed to define a delay across a module. It starts with specify and ends with the endspecify keyword. Inside the block the user can specify: specparam declaration, path declaration or system timing check.

This seems to imply it does not allow for-loops within specify blocks.

Hence it leads me to believe that you'll need to write out all the values one by one due to a limitation of the language.

One idea you could try is to restructure your modules to have a one bit input to a one bit output. Then each specify block will only have one delay to specify, and you can assign them each a random value. You can then generate these modules inside a generate block which will avoid you having to specify a delay for each bit manually.

However, this may be more tedious/awkward.

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