I want to divide two numbers(16-bit binary) in VHDL in 1 cycle (combinational circuit). Numerator is an integer. Denominator is a float. Result should be float. What algorithm do i use to perform the division.
Please help
2
-
1Do you need to do the division in one cycle, or to complete one division per cycle? Many floating point dividers are pipelined, so that they can produce a result per cycle without making the cycle time long enough to do a division in one cycle.Patricia Shanahan– Patricia Shanahan2013-10-04 01:44:15 +00:00Commented Oct 4, 2013 at 1:44
-
How long is your clock cycle?Martin Thompson– Martin Thompson2013-10-04 11:00:36 +00:00Commented Oct 4, 2013 at 11:00
Add a comment
|
2 Answers
Here is an entity that does what you want (if I understand the question correctly):
library ieee;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
entity integer_by_float_division is
port (
numerator: in signed(15 downto 0);
denominator: in signed(15 downto 0);
result: out float(6 downto -9)
);
end;
architecture rtl of integer_by_float_division is
subtype float16 is float(6 downto -9);
signal numerator_float: float16;
signal denominator_float: float16;
begin
numerator_float <= to_float(numerator, numerator_float);
denominator_float <= to_float(denominator, denominator_float);
result <= numerator_float / denominator_float;
end;
1 Comment
Martin Thompson
I think the OP means "IEEE754 single precision" when they said "float", so the denominator and out probably need to be
float32I don't think this is possible. Is there any reason that you need to do it in 1 clock cycle? The only way to get close would be to use a look-up table, but you would have to sacrifice some precision on the output.
