VHDL compiler error

Question

ERROR:HDLParsers:164 - "C:/.Xilinx/Counter/Main.vhd" Line 35. parse error, unexpected ENTITY, expecting COMMA or SEMICOLON

I don't know what error it pointing out... I am not able to see what it means, could someone clarify it for me..

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:52:28 03/05/2014 
-- Design Name: 
-- Module Name:    Main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;




entity Main is
PORT(
        CLK: in std_logic;
        LED: out std_logic_vector (7 downto 0)
        );

end Main;


architecture Behavioral of Main is
signal counter: std_logic_vector (7 downto 0);
signal prescaler:  std_logic_vector( 22 downto 0);
begin

CounterProcess: process(CLK)
begin
if rising_edge(CLK) then
    if prescaler < "1111111111111111111111" then 
        prescaler <= prescaler + 1;
        else
            prescaler <= (others => '0'); 
            counter <= counter + 1;
    end if;
end if; 
end process;

LED <= counter; 

end Behavioral;

Jim Lewis · Accepted Answer · 2014-03-06 00:27:03Z

2

WRT: ERROR:HDLParsers:164 - "C:/.Xilinx/Counter/Main.vhd" Line 35. parse error, unexpected ENTITY, expecting COMMA or SEMICOLON

The way you read this is the compiler died (errored out) when it found the keyword "ENTITY". It wanted to find either a ";" (as David explained for your case) or a ",".

answered Mar 6, 2014 at 0:27

Jim Lewis

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Comments

score 1 · Accepted Answer · 2014-03-06 01:33:27Z

1

You're missing a semicolon:

 use IEEE.STD_LOGIC_ARITH.ALL

after the use clause.

The reason why the VHDL analyzer complains way down there, is because that's where the next lexical token is found. Comments have no meaning to language analysis in VHDL, it would be clear to see if you removed them. The token string goes: reserved word ALL, reserved word ENTITY, in a place where lexical analysis would expect a semicolon for ending the use clause.

Theoretically the reserved word ALL is sufficient to tell you you're missing either a semicolon or comma as the next lexical token. That the distinction isn't made is a clue to parser implementation.

edited Mar 6, 2014 at 1:33

answered Mar 6, 2014 at 0:05

user1155120

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