Verilog Wave Forms

Question

I need to build a waveform from the following code:

module HW7P1 (A1, A0, B1, B0, O);
        input A1, A0, B1, B0;
        output O;
        assign O = (!A1 & B1) | (!A1 & !A0 & B0) | (!A0 & B1 & B0);
endmodule

module counter (clr, clk, OC);
        input clr, clk;
        output reg [3:0] OC;

        initial begin
                OC = 0;
        end

        always @(posedge clk) begin
                if (clr == 0)
                        OC = 0;
                else
                        OC = OC + 1;
        end
endmodule

module test_bench ();

wire HW7P1A1, HW7P1A0, HW7P1B1, HW7P1B0, HW7P1O;
wire clr, clk;
wire [3:0] counterO;
reg osc;


initial begin
osc = 0;
end

always begin
#10 osc = ~osc;
end


assign clr=1;
assign clk=osc;
counter C1(clr, clk, counterO);

assign HW7P1A1 = counterO[3];
assign HW7P1A0 = counterO[2];
assign HW7P1B1 = counterO[1];
assign HW7P1B0 = counterO[0];

HW7P1 P1(HW7P1A1, HW7P1A0, HW7P1B1, HW7P1B0, HW7P1O);

endmodule

I'd like to use EDA playground to do this since I don't have Verilog simulation software installed on my computer. However, when I select the "open EPWave after run" option, nothing seems to happen after I hit run. Can someone please tell me what I'm doing wrong?

Chiggs · Accepted Answer · 2014-03-26 22:10:52Z

7

Firstly you need to end the simulation, otherwise the sim will just run forever and eventually the process will get killed. You can do this by adding a call to $finish:

#10000 $finish

Secondly you need to create a VCD. Once you've added the above code EDAPlayground will give you a helpful error message:

No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?

So by adding the following code:

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
  #10000 $finish;
end

Your example code runs and is viewable in the waveform viewer: http://www.edaplayground.com/x/3v2

edited Mar 26, 2014 at 22:10

answered Mar 26, 2014 at 16:54

Chiggs

2,86424 silver badges32 bronze badges

Sign up to request clarification or add additional context in comments.

3 Comments

Victor Brunell Over a year ago

Great, thanks! Though I don't really understand the solution. Are there any good tutorials for beginners you can point me to? Also, why is the code placed all in the design section with nothing in the testbench section?

Chiggs Over a year ago

@Caulibrot They were all in one section because I was just lazy and copy'n'pasted your code into a window. I've updated the playground to split it out. I don't know of any particularly "good" tutorials, they all seem to be pretty similar to me!

Victor Brunell Over a year ago

Thanks Chiggs. That was a big help.

Collectives™ on Stack Overflow

Verilog Wave Forms

1 Answer 1

3 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

3 Comments

Your Answer

Sign up or log in

Post as a guest

Related