How to try cache invalidation and cache clean in ARM?

Question

I want to try cache clean and cache invalidate in Raspberry Pi Can someone guide on this. I just want to do some DMA transfer and try some stuff.

Also if some one can give me a code snippet on how to check if cache has been cleaned in ARM It will be really helpfull

For Eg. I want to see state of cache memory and give instruction Cache invalidate and see the state of memory

Marco Bonelli · Accepted Answer · 2020-11-11 15:00:47Z

4

For the Raspberry Pi's ARM1176, cache maintenance is performed via the c7 group of System Control Coprocessor (CP15) operations. Data cache clean+invalidate is mcr p15, 0, r0, c7, c14, 0, and the Cache Dirty Status Register (which simply tells you if the cache is clean or has been written to) can be read with mrc p15, 0, <Rd>, c7, c10, 6.

There's too much information to regurgitate here, so I'd recommend referring to the TRM for the details - if the Raspberry Pi TRM doesn't cover it, you can find the full ARM1176 TRM here (which contains a few example code snippets). As always, the Linux source also provides a handy real-world usage reference.

As for inspecting the actual cache contents, AFAIK you're going to need a JTAG hardware debugger for that, if at all.

edited Nov 11, 2020 at 15:00

Marco Bonelli

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answered Aug 13, 2014 at 8:30

Notlikethat

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3 Comments

artless-noise-bye-due2AI Over a year ago

The C15 (not CP15) is usually very ARM specific and sometimes allows cache inspection. The ARM1176 doesn't seem to have this. You can inspect the cache by exploiting incoherency. 1. turning off the cache 2. complement one memory word/line 3. turn on the cache 4. read the memory. This will work for a region up to the cache size. You can revert the memory back to the original state after this.

Notlikethat Over a year ago

@artlessnoise I've not heard C15 before - all ARM's documentation refers to coprocessors as CPn. I like that trick, but if the region wasn't in the cache then you'll never know what was. And it doesn't help for the I cache (not that that would be particularly interesting, admittedly). Plus, y'know, all the many ways incoherency can go wrong ;)

artless-noise-bye-due2AI Over a year ago

I mean mrc p15, 0, <Rd>, c15, cxx, n is a reserved cp15 space. Yes, I meant if you have a 32K d-cache you can inspect 32K of main memory to say was it cached? With a yes/no answer for each line. Slightly better than impossible.

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