How do I initialize the array Save_state? This statement is giving X value at the output:
reg [9:0] count
reg [9:0] Save_state [0: 1024];
always @ (posedge Clock )
Count <=count+1 ;
Save_state[count] <=count ;
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2 Answers
You can use an initial block as well. This is allowed in simulation and is synthesizable on some architectures (Xilinx FPGA and CPLD support register initialization)
reg [9:0] count
reg [9:0] Save_state [0: 1024];
integer i;
initial begin
count = 0;
for (i=0;i<=1024;i=i+1)
Save_state[i] = 0;
end
always @ (posedge Clock ) begin
count <= count + 1;
Save_state[count] <= count;
end
Although for this particular example, in which the elements of the Save_state array will always have the same value, you can do like this (synthesizable on Xilinx and Altera, AFAIK):
reg [9:0] Save_state [0: 1024];
integer i;
initial begin
for (i=0;i<=1024;i=i+1)
Save_state[i] = i[9:0];
end
And at the beginning of you simulation, Save_state already have the values 0,1,2,...,1023 stored in it.
Comments
You can use a reset port to initialize count and save_state such as the following code :
integer i;
reg [9:0] count;
reg [9:0] save_state [0:1024];
always @(posedge clock or posedge reset) begin
if (reset) begin
count <= 0;
for (i=0; i<=1024; i=i+1)
save_state[i] <= 0;
end
else begin
count <= count + 1;
save_state[count] <= count;
end
end
The two statements inside the else block is applied at the same time and at the end of always block.
2 Comments
mcleod_ideafix
If you use non-blocking assigment both statements on the else block are applied at the same time
Amir
Yes, thanks. Both statements inside the
else block is applied at the same time and at the end of always block.