verilog if-statement hardware translation

Question

I am trying to reduce my critical path and found the following confusing

          if(counter > 14) begin
             state <= ROUND1;
          end if(offset > message_size) begin
             state <= READ2;
          end

After doing TimeQuest in Quartus, I got back the hardware translation of

enter image description here

The 4 blue blocks on the left are the less than comparison operator for offset > message_size. I am wonder why there are 4 of them and why is it "LessThanX~Y" instead of greater than? The offset and message_size are both 32-bits and they are inside of always@(posedge clk) of a case-statement.

Is there a more optimal way to write this if-statement to reduce my critical path?

Did you try to use else if instead of if ? (second if) — Amir
– Amir, Commented Mar 15, 2015 at 5:13

Jithin · Accepted Answer · 2015-03-15 07:05:03Z

1

Use always @* to make sure all signals are in the sensitivity list.When the sensitivity list does not contain a signal used in the code, that code will generate latches.

Use else instead of using if statement again.

edited Mar 15, 2015 at 7:05

answered Mar 15, 2015 at 6:42

Jithin

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Comments

Barry Moss · Accepted Answer · 2015-03-16 17:55:46Z

A 32-bit comparison is going to take several 6-input LUTs to realize, so the amount of logic doesn't surprise me. It does seem like there are a lot of signals missing in your schematic, but perhaps that's just because you are showing only the critical path. A less than block is the same as a greater than block just with the inputs reversed. I agree with the previous comments that your "end if" should be replaced by an "else if".

Now reducing the critical path is just a matter of pipelining. The first thing I would try is to register the result of the two greater than comparisons before using them in the state machine code. You could also break up your larger comparison into two stages -- compare both the upper and lower 16 bits in parallel during cycle 1 and the use the results in the second cycle to complete the 32-bit compare.

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