Array with dynamic length for simulation

Question

In VHDL, is there a way to have a dynamically sized array for simulation?

I would like to use it as a list, i.e., the testbench repeatedly appends values to the end, and then iterates over the list. The length of the array is not statically known.

Yes. The easiest way is to determine the length at runtime, refer to the array via an access type (pointer) and allocate it with new. If it needs to continually grow, you will need to reallocate,copy atd free the old one. — user1818839
– user1818839, Commented Aug 3, 2015 at 13:54
But note that you can't create signals this way - only variables. — EML
– EML, Commented Aug 3, 2015 at 16:45

Fosfor · Accepted Answer · 2019-04-15 12:08:33Z

3

The array utility of VUnit (https://github.com/VUnit/vunit/tree/master/vunit/vhdl/array) provides the functionality you're looking for. It provides a protected type array_t which has a method append that does the dynamic sizing. Here is some code from the testbench for this utility (https://github.com/VUnit/vunit/blob/master/vunit/vhdl/array/test/tb_array.vhd) that exemplifies the append method

variable arr : array_t;
...
arr.init;
...
arr.append(11);
check_equal(arr.length, 1);
check_equal(arr.get(0), 11);

arr.append(7);
check_equal(arr.length, 2);
check_equal(arr.get(1), 7);

edited Apr 15, 2019 at 12:08

Fosfor

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answered Aug 3, 2015 at 19:39

lasplund

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1 Comment

Adrian Willenbücher Over a year ago

Update: This type is now called integer_array_t

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