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I wanted to make a 2bit comparator using VHDL. I have the following architecture:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity eq2 is
    Port ( a : in  STD_LOGIC_VECTOR (1 downto 0);
           b : in  STD_LOGIC_VECTOR (1 downto 0);
           aeqb : out  STD_LOGIC);
end eq2;


architecture struc_arch of eq2 is
signal e0,e1 : std_logic ; 

begin
eq_bit0_unit  : entity work.eq1(sop_arch); 
port map (i0=>a(0) , i1=> b(0) , eq=>e0);

eq_bit1_unit : entity work.eq1(sop_arch); 
port map (i0=>a(1),i1=>b(1),eq=>e1);
aeqb <= e0 and e1;
end struc_arch ;

This architecture obviously depends on eq1 entity. Here is my lab1 entity and architecture:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity eq1 is
    Port ( i0 : in  STD_LOGIC  ;
           i1 : in  STD_LOGIC;
           eq : out  STD_LOGIC);
end eq1;


architecture sop_arch of eq1 is
signal p0,p1 : std_logic;
begin

p0<= (not i0) and (not i1);
p1<= not i0 and i1;
eq <= p0 and p1;

end sop_arch;

I am getting the following error:

  • List item ERROR:HDLParsers:3324 - "C:/Users/user/Documents/tp_vhdl/studies/eq2.vhd" Line 16. IN mode Formal i0 of entity with no default value must be associated with an actual value.
  • List item ERROR:HDLParsers:164 - "C:/Users/user/Documents/tp_vhdl/studies/eq2.vhd" Line 17. parse error, unexpected PORT

I tried the solutions on this link but it didn't work either : VHDL - Assigning Default Values

1 Answer 1

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The second error gives you the solution to this problem.

Unexpected PORT

This line looks correct at first glance, but look carefully at the previous line:

eq_bit1_unit : entity work.eq1(sop_arch); -- extra semicolon, oops! 
port map (i0=>a(1),i1=>b(1),eq=>e1);

So you are trying to instantiate an eq1, with no port map. It tries to instantiate with default assignments, but there are none, hence the first error. It then gets to the second line (line 17), and it's seeing an expression start with the keyword port, which is not valid, hence the second error.

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