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As I know, nowadays the 'reg' type in systemverilog can used in assign statement.

In old fashion, the assign statement does use the only the 'net' type.

So I want to know that what kind of the signals are should have to be the 'net' type in systemverilog?

Update1

From here, http://www.testbench.in/IF_01_INTERFACE.html I can find a interface declaration.

interface intf #(parameter BW = 8)(input clk); 
logic read, enable; 
logic [BW -1 :0] addr,data; 
endinterface :intf 

At this here, I want to know that why the read and enable and addr and data signal are clared logic data type? Is there any reason? Why not used reg or wire?

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A net is used when there are multiple drivers on a signal, usually in conjunction with a bi-directional port, and for designs at the switch level that require strength to operate. See "What’s the deal with those wire’s and reg’s in Verilog" for more details.

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Regarding the usage of net Dave's answer pretty much covers it.

From the IEEE Std 1800-2012,

The keyword reg does not always accurately describe user intent, as it could be perceived to imply a hardware register. The keyword logic is a more descriptive term. logic and reg denote the same type.

More info on the usage of logic can be found in below links.

1) Morgans answer

2) Greg's answer

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