default nettype only for inputs

Is it possible to have wire as default for inputs, but not default declare module internal signals?

As I understand `default_nettype` controls

1. port kind of input and inout ports (As discussed in Question Implicit net-type declaration and `default-nettype)
2. kind for signals in the design (for example logic)

Example, setting `default_nettype wire makes this code

module m1 (
   input  logic i1,
   output logic o1
   );

   logic  l1;
   assign l1 = i1;
   assign o1 = l1;
endmodule

mean the same thing as:

module m1 (
   input  wire logic i1,    // <-- default wire
   output logic o1
   );

   wire logic l1;          // <-- default wire
   assign l1 = i1;
   assign o1 = l1;
endmodule

Is there some setting that allows input to get default nettype wire but still cause failure in the case when an undefined signal is used:

module m1 (
   input  logic i1,   // <-- let this one default to wire
   output logic o1
   );

   logic  l1;
   logic banana;
   assign l1 = i1;
   assign hanana = i1;   // typo, should give error since no default declaration
   assign o1 = l1;
endmodule