Verilog operation unexpected result

Question

I am studying verilog language and faced problems.

integer intA;
...
intA = - 4'd12 / 3; // expression result is 1431655761.
                    // -4’d12 is effectively a 32-bit reg data type

This snippet from standard and it blew our minds. The standard says that 4d12 - is a 4 bit number 1100. Then -4d12 = 0100. It's okay now.

To perform the division, we need to bring the number to the same size. 4 to 32 bit. The number of bits -4'd12 - is unsigned, then it should be equal to 32'b0000...0100, but it equal to 32'b1111...10100. Not ok, but next step.

My version of division: -4d12 / 3 = 32'b0000...0100 / 32'b0000...0011 = 1

Standart version: - 4'd12 / 3 = 1431655761

Can anyone tell why? Why 4 bit number keeps extra bits?

dave_59 · Accepted Answer · 2016-06-17 15:28:09Z

4

You need to read section 11.8.2 Steps for evaluating an expression of the 1800-2012 LRM. They key piece you are missing is that the operand is 4'd12 and that it is sized to 32 bits as an unsigned value before the unary - operator is applied.

If you want the 4-bit value treated as a signed -3, then you need to write

intA = - 4'sd12 / 3 // result is 1

answered Jun 17, 2016 at 15:28

dave_59

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Comments

Ajith S · Accepted Answer · 2022-01-18 17:11:08Z

0

here the parser interprets -'d12 as 32 bits number which is unsigned initially and the negative sign would result in the negation of bits. so the result would be

negation of ('d12)= negation of (28 zeros + 1100)= 28ones+2zeros+2ones = 11111111111111111111111111110011. gives output to 4294967283 . if you divide this number (4294967283) by 3 the answer would be 1,431,655,761.

keep smiling :)

answered Jan 18, 2022 at 17:11

Ajith S

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