Verilog code motion estimator

Question

I having trouble with finding the smallest values of X and xfind and Y and yfind in `Costcalculator xfind (X,xcost); Costcalculator yfind (Y,ycost);

in code below. can someone comment please. For some reason I couldn't import the whole code. It just recognizes these lines as codes. Sorry if it is not clear.

  always @(posedge clk)   // sequential circuit

  begin

    Costcalculator xfind (X,xcost);
    Costcalculator yfind (Y,ycost); 

    if(reset)
      begin 
        i=0;
        R<=0;
        xcost<=0;
        ycost<=0;
        mode0<=0;
        mode1<=0;
        mode2<=0;
        mode3<=0;
        mode4<=0;
        mode5<=0;
        mode6<=0;
      end   //if end
        else
      begin
            for (i=1; i<43;  i=i+1)
      begin
               R<=xcost+ycost;
         costholder <= SAD+(lambda*R);   // Here we calculate the cost of a sub-blocks As the clock
                if (i<17)
         mode0<=costholder+mode0;
       else if(i>16 && i<25)
         mode1<=costholder+mode1;
       else if(i>24 && i<33) 
         mode2<=costholder+mode2;
       else if(i==33 || i==34 || i==35 || i==36 )
         mode3<=costholder+mode3;
       else if(i==37 || i==38)
         mode4<=costholder+mode4;
       else if(i==39 || i==40)
         mode5<=costholder+mode5;
       else if(i==41)
         mode6<=costholder+mode6;

       end    //for end
    end   //else end
  end   //always end

Module Costcalculator:

//**********************************************************‌** 
module Costcalculator (motionvector, cost); // X AND Y COST CALCULATOR 
input [4:0]motionvector; 
output [2:0]cost; 
reg [2:0]cos; 
wire [3:0] vector; 
assign vector = {motionvector[3:0] }; 

always @* begin 
case (vector) 0 : cos=0; 
1,2 : cos=1; 
3,4,5,6 : cos=2; 
7,8,9,10,11,12,13,14 : cos=3; 
15 : cos=4; 
endcase 
end 
assign cost = cos; 
endmodule 
//**********************************************************‌**

What is the error? I believe Constcalculator is a module. You can not instantiate a module in a procedural block. — sharvil111
– sharvil111, Commented Sep 3, 2016 at 1:41
You should try to 1) make a minimal (not) working design, 2) make sure we have all relevant code and 3) provide a clue about what's wrong. So you should remove all irrelevant code, tell us what is "Costcalculator", probably a module as pointed out by sharvil111 considering the syntax you used and 3) give us the error code/tell us what is wrong? Impossible to answer otherwise ... — chrisvp
– chrisvp, Commented Sep 3, 2016 at 15:31
//************************************************************ module Costcalculator (motionvector, cost); // X AND Y COST CALCULATOR input [4:0]motionvector; output [2:0]cost; reg [2:0]cos; wire [3:0] vector; assign vector = {motionvector[3:0] }; always @* begin case (vector) 0 : cos=0; 1,2 : cos=1; 3,4,5,6 : cos=2; 7,8,9,10,11,12,13,14 : cos=3; 15 : cos=4; endcase end assign cost = cos; endmodule //************************************************************ — Aliyar Attaran
– Aliyar Attaran, Commented Sep 4, 2016 at 22:45
It gives the syntax error: Error-Stack Exchange Syntax error Following verilog source has syntax error : "design.sv", 97: token is '(' Costcalculator xfind (X,xcost); ^ — Aliyar Attaran
– Aliyar Attaran, Commented Sep 4, 2016 at 22:48

Community · Accepted Answer · 2017-05-23 11:51:45Z

1

After taking the module outside the always block, you are driving xconst and yconst from two places. On the other hand, I don't see drivers of X and Y.

Since Costcalculator is a purely combinational module, you need to just provide the inputs X and Y as zero from the top/wrapper module.

//.. some stuff
if(reset) begin
//... some other signals
X <= 0;
Y <=0;
//...

As the error says about multiple drivers, you are driving xconst and yconst form two modules. On reset, if you provide X and Y as 0 from the wrapping module, then automatically the vector will go to Zero and ultimately the cost which is the output of module will become Zero. Thereby the variables xconst and yconst will become zero.

Refer to this similar forum question for more information.

edited May 23, 2017 at 11:51

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answered Sep 5, 2016 at 3:51

sharvil111

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