Verilog: Using reg As Counters For for-loops

Question

In a module:

reg a, b;
integer i, j;

initial
     begin
          for (a = 0; a < 2; a = a + 1)     
               //some code
     end

The textbook says it would be incorrect to get rid of integers i and j and use reg a and b directly as loop counters. Hint: reg variables have a fixed size and, hence, they wrap.

What does that mean? Doesn't integer have a fixed size as well? And what's wrapping?

google.co.uk/search?q=integer+wrapping

Oliver Charlesworth
– Oliver Charlesworth

2017-06-19 23:31:14 +00:00
Commented Jun 19, 2017 at 23:31 — Oliver Charlesworth
– Oliver Charlesworth, Commented Jun 19, 2017 at 23:31

Ari · Accepted Answer · 2017-06-20 00:21:21Z

2

A reg is either single bit, or multiple bit if you define it as an array. An integer, on the other hand is 32 bits. So if you have a loop, it is more convenient to use an integer variable that doesn't overflow as the loop advances.

In your example, you set a < 2, so with a single bit reg the loop never terminates.

Moreover integers are singed values.

edited Jun 20, 2017 at 0:21

answered Jun 19, 2017 at 23:59

Ari

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1 Comment

Serge Over a year ago

integer is 32 bit in verilog, never 64. Single-bit reg will overflow and loop will never exit. You need at least 2-bit reg.

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