Can Dynamic array be used inside generate for loop in systemverilog

Question

While passing the dynamic variable member as port in generate for loop instantiation,

int clk[];

initial begin
  N=clk.size(); 
end

initial begin
  clk=new[4];
end

always @(*) begin 
  clk[0]=clk0_out;
  clk[1]=clk1_out;
  clk[2]=clk2_out;
  clk[3]=clk3_out;
end 

genvar i;
generate    
  for(i=0;i<N;i=i+1)  begin: monitor_call 
    clock_mon cm1(.clock(clk[i]),.reset(reset));
  end  
endgenerate

following errors occurred:

Illegal non-constant generate loop condition.

A member of a dynamic variable (clk) is not allowed as a port actual.

While passing static array as port inside generate loop instantiation, there were no such errors. Why is there problems with dynamic array?

Can't they be used inside generate loop? If not, what is the alternative for the same as I want to instantiate the module 'n' times?

Matthew · Accepted Answer · 2018-06-20 12:47:11Z

0

The size of a static array is fixed at compile time. The size of a dynamic array is fixed at run time (and can be changed at run time, too).

The bounds of a generate loop must be static. That is, they must be fixed at compile time. The reason why is obvious if you think about it: the bounds of a generate loop control how much hardware is simulated or synthesised. You cannot have a circuit whose size can vary according to some input.

So, you need to make your array and the bounds of your generate loop static. That is, you need to fix the size of the array and the bounds of the generate loop at compile time.

answered Jun 20, 2018 at 12:47

Matthew

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2 Comments

Nupur Over a year ago

Thankyou for the answer. But I need to use the dynamic array and want to instantiate a module 'N' times. But in that case generate loop can't be used, so is there any alternate for this?

Matthew Over a year ago

No. N must be static (a literal, a parameter, a localparam). You cannot vary the amount of hardware dynamically. Why not make N a localparam and use a static array?

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