Zynq + Microblaze share DDR memory via smart interconnect

Question

I have a block design with a Zynq and Microblaze on an Xilinx Zed board.

I want the microblaze to be able to access DDR memory shared with the arm corers in the PS. My microblaze uses a cache. There are two AXI ports on the microblaze M_AXI_DC, M_AXI_IC that need to be connected so that they have access to the PS DDR memory.

The microblaze ports are AXI4, Zynq uses AXI3. How to connect M_AXI_DC, M_AXI_IC?

2.1. A shared smart interconnect for both IC and DC ports?

     mb M_AXI_DC, M_AXI_IC <-smart interconnect-> S_AXI_HP0

or

2.2. Two separate smart interconnects for the ports?

     mb M_AXI_DC <-smart interconnect 1-> S_AXI_HP0 zynq 

     mb M_AXI_IC <-smart interconnect 2-> S_AXI_HP1 zynq

or maybe

2.3. One smart interconnect connected to HP0 and HP1:

     mb M_AXI_DC                         S_AXI_HP0 zynq
              <-smart interconnect 1->            
     mb M_AXI_IC                         S_AXI_HP1 zynq

2.3. Does approach 2.1, 2.2 or 2.3 differ in performance?

Edward Kigwana · Accepted Answer · 2019-02-26 21:04:44Z

2

Approach 2.3 is most efficient use of PL resources for cache access. Think of the interconnect as a router. You need one for the Cache ports and a separate one for the peripherals.

What you seem to have left off is the DP port. That port is how data moves from DDR to the mb. If you move a lot data, then you have use a DMA instead.

See xapp1093 Page 3 Figure 1. has a diagram showing a complete design with code.

answered Feb 26, 2019 at 21:04

Edward Kigwana

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4 Comments

dwjbosman Over a year ago

Indeed DP was not mentioned. The DP was already connected to a separate axi smartconnect that is connected to a.o .gpio,

dwjbosman Over a year ago

In an earlier test, I had a standalone Microblaze which had one interconnect . On the microblaze side the interconnect was attached to DP, DC,IC on the other end the interconnect was attached to MIG DDR, gpio, ethernet. What kind of impact will it have to route the DP through the same interconnect as DC and IC?

Edward Kigwana Over a year ago

Look at pg059-axi-inteconnect pg.6. Each interconnect has a single Crossbar with selectable interconnect architecture. The interconnect cannot know that data on port S00 is destined only for M00 so some switching overhead. Doing this will create a bottleneck because program instructions and data are routed through the same interconnect. The optimal configuration is to keep those separate. Also, note that you provided an incomplete picture of your setup. Do you have DDR attached directly to the PL that you already access via the MIG interface and now want to access the Zynq DDR?

dwjbosman Over a year ago

Sorry for the confusion, I meant that in another design (not Zynq,but Artix7, Nexys4ddr) I had a Microblaze connected MIG DDR where all the axi interfaces of the Microblaze were routed via a single interconnect. Although this worked, I have no idea what kind of performance impact to expect. So for my current Zynq design I will go for the architecture as described in xapp1093.

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