VHDL mux implementation?

Question

Is it possible to implement a mux with multiple control signals? For example, I want to do something like this:

with (sig1 & sig2) select  
output <= A when "00",  
B when "01",  
C when "10",  
D when "11",  
'0' when others;

I know I could just assign them to a new signal and use that, but that's something I want to avoid if possible.

Can you explain why this is a MUX? It looks like have implemented the behavior of a logic XOR. — Philippe
– Philippe, Commented Apr 12, 2011 at 15:09
It was just a general example. For more complex things with more than two signals it gets harder to figure out whats going with logic equations. — Jonathan D
– Jonathan D, Commented Apr 14, 2011 at 8:52

Martin Thompson · Accepted Answer · 2011-04-14 14:26:34Z

3

You need to enable VHDL2008 mode on your compiler to have it work.

An alternative (also 2008):

muxing: process (sig1, sig2) is
begin  -- process muxing
    case sig1 & sig2 is
        when "00" => output <= '1';
        when "01" => output <= '0';
        when "10" => output <= '0';
        when "11" => output <= '1';
        when others => output <= '0';
    end case;
end process muxing;

If you have no VHDL-2008 mode on your compiler it will fail with complaints of

Array type case expression must be of a locally static subtype.

or similar.

If your compiler can't be made to be VHDL-2008 compliant, you have to work around this by creating a type that you can use to surround the sig1 & sig2 to explicitly tell the compiler what's going on:

subtype twobits is bit_vector(0 to 1);

Then:

with twobits'(sig1 & sig2) select  
    output <= '1' when "00",  
    -- etc.

or:

case twobits'(sig1 & sig2) is
     when "00" =>  -- etc.

edited Apr 14, 2011 at 14:26

answered Apr 11, 2011 at 12:16

Martin Thompson

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2 Comments

Jonathan D Over a year ago

Hi, thanks for the reply, but what do you mean by "creating a type"? I'm getting this error: "Ambiguous type in infix expression; ieee.std_logic_1164.std_ulogic_vector or ieee.std_logic_1164.std_logic_vector. String literal found where non-array type (error) was expected." Sorry about the formatting, new here. Also, is there a purely dataflow way of doing this?

Martin Thompson Over a year ago

@Jonathan D: Updated to answer those queries. You should be able to keep you original code if you want dataflow. For your "ambiguous type in infix expression" that sounds like a different problem, post a new question

edgarmtze · Accepted Answer · 2011-04-10 04:59:50Z

1

See this, maybe it helps you

entity MUX is
  port ( a, i0, i1 : in bit;
         o : out bit );
end MUX;

architecture behave of MUX is
begin
  process ( a, i0, i1 ) begin
    if  a = '1'  then
      o <= i1;
    else
      o <= i0;
    end if;
end process;
end behave;

answered Apr 10, 2011 at 4:59

edgarmtze

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