Simplify combinational logic using yosys

Question

I am wondering if it is possible to use Yosys in simplifying logic equations.

For example:

module top
(
    output [31:0] cipher,
    input  [31:0] plain,
    input  [63:0] key
);

    wire tmp = key[31:0];
    wire tmp2 = key[63:32] & 0;

    assign cipher = (tmp & plain) | tmp2;

endmodule

When I use the command "show" it plots the circuit:

I tried using "opt" and "freduce" commands but it did not reduce the equation.

gatecat · Accepted Answer · 2019-08-01 19:06:52Z

1

You probably want to use opt -fine which does finer-grain optimisations rather than optimising whole words at a time. This gives a single 1-bit $and gate as expected.

Alternatively techmap; abc will produce an optimised gate-level circuit.

answered Aug 1, 2019 at 19:06

gatecat

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