verilog assignment compiler error

Question

I have a basic compiler error I am not able to figure out. Code:

module (input [127:0] in1,
        input [2:0] en);
real a1;
if(en==3'b001)
begin
  a1=$bitstoreal(in1[31:0]);
end

The error is :

Error: E:/Modeltech_pe_edu_10.0/examples/FloatingPt.v(20): near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER or '#' or '('

user597225 · Accepted Answer · 2011-04-23 18:21:48Z

3

You have procedural code outside a procedural construct.

real a1;
initial
  begin
  if(en==3'b001)
    begin
    a1=$bitstoreal(in1[31:0]);
    end
  end

answered Apr 23, 2011 at 18:21

user597225

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3 Comments

Brahadeesh Over a year ago

I dont want it inside an initial block. Is there any other way to do it?

user597225 Over a year ago

Yes. Use a task or a function.

user597225 Over a year ago

Take a look at this memory model. micron.com/get-document/?documentId=5243 -> Sim Models -> LPDDR Verilog Model. The model is mobile_ddr.v You can see how the model uses a few procedural blocks for high-level control and then calls tasks containing groups of calculations.

Marty · Accepted Answer · 2011-04-23 18:21:50Z

3

Assignments in Verilog are done by the assign statement if you're trying to set the value of a wire or within a procedural block (always or initial) for other data types.

In your example, you are missing an always block:

always @(*) begin
    if(en==3'b001) begin
        a1=$bitstoreal(in1[31:0]);
    end
end

You also might have a problem assigning a bus to the real type if you're not sure of what you're doing. You might need to write it as a1 = $itor(in1);

answered Apr 23, 2011 at 18:21

Marty

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2 Comments

Brahadeesh Over a year ago

If I dont want to include an always block, how do i do it?

Brahadeesh Over a year ago

its not possible to do continuous assignment for real types. I think they are implemented as registers.

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