Implementing a for loop in systemverilog

Question

I want to generate an automated input stimulus for my DUT. This input is going to different modules at the same time and working on this data. I want my input to be generated in an increasing manner. Like 0000,0001,0010,0011...1111 I tried using a for loop but it only uses the last data from the loop and works on that.

always_comb begin
  for (i=0, i<16; i=i+1)
  begin 
    data <= i;
  end 
end

When I give inputs individually like,

data = 8'd1;
#2;
data = 8'd2;
#2;

It works smoothly with all input values specified.

Greg · Accepted Answer · 2019-08-30 17:01:47Z

2

always_comb cannot have delays. At least per the IEEE1800 standard.

You can do something like this:

bit [3:0] data; // bit so the initial value is 0, not x
bit clk;
always #1 clk++; // or some other clock model
always_ff @(posedge clk) begin
  data <= data+1;
end

or something like this:

logic [3:0] data;
initial begin
  for (i=0, i<16; i=i+1) begin 
    data = i;
    #2;
  end 
end

Or some other similar code with time delay.

answered Aug 30, 2019 at 17:01

Greg

19.3k6 gold badges51 silver badges72 bronze badges

Sign up to request clarification or add additional context in comments.

4 Comments

Rucha R Over a year ago

Is there some way to do this process using constraints?

Greg Over a year ago

Not sure what you mean by "constraints"; SystemVerilog randomization constraint constructs or something else.

Rucha R Over a year ago

Yes. That is exactly what I meant.

Greg Over a year ago

There is nothing preventing you if implement correctly. How to implement depends on they use case and desired behavior.

Collectives™ on Stack Overflow

Implementing a for loop in systemverilog

1 Answer 1

4 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

4 Comments

Your Answer

Sign up or log in

Post as a guest

Related