Setting the mstatus register for RISC-V

Question

I am trying to load mstatus with another register t1.

 lw t1, mstatus              # load mstatys register into t1
 xori t1, t1, 0x8            # xor mstatus to set 3rd bit and leave everything else as is
 lw mstatus, t1              # set mstatus

The initial lw t1, mstatus works just fine. However when trying to lw mstatus, t1 the assembler gives

Error: illegal operands 'lw mstatus, t1'

I have no idea what causes this error, mstatus register is a read/write register. It should work.

Are you trying to set 3rd bit (as the comment says), or to toggle it? Because ori would be the correct instruction for setting (xori would be for toggling, so its use is inconsistent with the comment). — Dato
– Dato, Commented Dec 30, 2019 at 16:51

Ömer GÜZEL · Accepted Answer · 2023-03-06 07:58:38Z

7

mstatus is not a memory part. Then it can't be loaded/stored with lw/sw instructions under general purpose registers (x1-x31).

mstatus is part of CSR (Control Status Registers) that been accessed with Control and Status Register Instruction (see chapter 2.8 of riscv-spec).

Then to load mstatus you should use csrrs/c instruction and to write csrrw instruction depending of what you want to do you can also just clear/set individual bit of register.

Write t1 in mstatus and don't care of mstatus old value (x0):

csrrw t1, mstatus, x0

Read mstatus in t1 and don't touch mstatus value:

csrrs x0, mstatus, t1

or

csrrc x0, mstatus, t1

edited Mar 6, 2023 at 7:58

Ömer GÜZEL

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answered Dec 30, 2019 at 9:10

FabienM

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Comments

Xypron · Accepted Answer · 2020-08-09 19:50:10Z

5

In addition to @FabienM‘s answer, I would add a reference to the pseudo instructions for handling CSRs. E.g. csrr rd, csr which is short for csrrs rd, csr, x0 and simply reads the given CSR. Those can be found in chapter 9.1 "CSR Instructions", of the The RISC-V Instruction Set Manual Volume I: Unprivileged ISA.

edited Aug 9, 2020 at 19:50

Xypron

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answered Jan 1, 2020 at 11:03

Joachim Lusiardi

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