Assigning values to parametrized arrays in Verilog

Question

Suppose I have the following module definition,

module foo(b)
input b;
parameter length = 8;

reg [length-1:0] dummy ;

Now, I want to assign values to this dummy array. For instance I want to make it all 1s. If the length was not parameterized, I could do this,

always @(posedge b)
 dummy <= 8'hFF;

But when the length is parameterized, I would hope to do this,

always @(posedge b)
 dummy <= length'hFFFF //won't even compile. even if it did, how many F's should there be?

How can I assign ones (or zeroes) to an entire array whose length is parameterized? Or more generally, how can I assign values while specifing the length of a parameterized array?

Do you really mean packed arrays? reg [length-1:0] dummy; Your declaration was unpacked, and you cannot have those kind of assignments to unpacked array, parameterized or not. — dave_59
– dave_59, Commented Jul 30, 2020 at 18:45

m4j0rt0m · Accepted Answer · 2020-07-30 20:10:24Z

5

You can do bit extension:

always @ (posedge b)
  dummy <= {length{1'b1}};

What is inside the {} is extended by "parameter-1", would be the same as having:

always @ (posedge b)
  dummy <= {1'b1,1'b1,1'b1,1'b1....};

answered Jul 30, 2020 at 20:10

m4j0rt0m

3541 silver badge5 bronze badges

Sign up to request clarification or add additional context in comments.

Comments

dave_59 · Accepted Answer · 2020-07-30 18:57:57Z

1

You can write

always @(posedge b)
 dummy <= ~1'b0;

This takes advantage of the fact that Verilog extends operands before applying operators when they are in context-determined expressions.

In SystemVerilog, you can write

always @(posedge b)
 dummy <= '1;

edited Jul 30, 2020 at 18:57

answered Jul 30, 2020 at 18:55

dave_59

43.3k3 gold badges29 silver badges66 bronze badges

2 Comments

zeke Over a year ago

What difference would writing dummy <= ~0; make, if any?

dave_59 Over a year ago

No difference in this expression. But do realize that 0 is the same as writing 32'sd0

Collectives™ on Stack Overflow

Assigning values to parametrized arrays in Verilog

2 Answers 2

Comments

2 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

2 Answers 2

Comments

2 Comments

Your Answer

Sign up or log in

Post as a guest

Related