why I get Syntax error near "else" in assertion in verilog?

Question

I am trying to run a testbench which was written for a neuromorphic chip named ODIN. Irun this code in Xilinx ISE. I get some errors that do not make sense. here is a part of code:

$display("----- Starting verification of programmed SNN parameters");
    assert(snn_0.spi_slave_0.SPI_GATE_ACTIVITY ==  1'b1) else $fatal(0, "SPI_GATE_ACTIVITY parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_OPEN_LOOP              == `SPI_OPEN_LOOP             ) else $fatal(0, "SPI_OPEN_LOOP parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_SYN_SIGN               == `SPI_SYN_SIGN              ) else $fatal(0, "SPI_SYN_SIGN parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_BURST_TIMEREF          == `SPI_BURST_TIMEREF         ) else $fatal(0, "SPI_BURST_TIMEREF parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_OUT_AER_MONITOR_EN     == `SPI_OUT_AER_MONITOR_EN    ) else $fatal(0, "SPI_OUT_AER_MONITOR_EN parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_AER_SRC_CTRL_nNEUR     == `SPI_AER_SRC_CTRL_nNEUR    ) else $fatal(0, "SPI_AER_SRC_CTRL_nNEUR parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_MONITOR_NEUR_ADDR      == `SPI_MONITOR_NEUR_ADDR     ) else $fatal(0, "SPI_MONITOR_NEUR_ADDR parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_MONITOR_SYN_ADDR       == `SPI_MONITOR_SYN_ADDR      ) else $fatal(0, "SPI_MONITOR_SYN_ADDR parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_UPDATE_UNMAPPED_SYN    == `SPI_UPDATE_UNMAPPED_SYN   ) else $fatal(0, "SPI_UPDATE_UNMAPPED_SYN parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_PROPAGATE_UNMAPPED_SYN == `SPI_PROPAGATE_UNMAPPED_SYN) else $fatal(0, "SPI_PROPAGATE_UNMAPPED_SYN parameter not correct.");
    assert(snn_0.spi_slave_0.SPI_SDSP_ON_SYN_STIM       == `SPI_SDSP_ON_SYN_STIM      ) else $fatal(0, "SPI_SDSP_ON_SYN_STIM parameter not correct.");

I get this error for each line:

Syntax error near "else".

Some tools need user add something like -sv explicitly on the command line to tell the tool there's systemverilog in the design code. I'm not familiar with Xilinx ISE. — Light
– Light, Commented Aug 23, 2020 at 12:52
Xilinx ISE doesn't support System verilog language .. Use Vivado tool for ur simulations — Rama Krishna Meda
– Rama Krishna Meda, Commented Aug 23, 2020 at 14:28
I cant use vivado, is there any way to change the syntax in a way that is appropriate? — dreamer1375
– dreamer1375, Commented Aug 23, 2020 at 18:15

Serge · Accepted Answer · 2020-08-23 18:29:44Z

1

In our simple case for simulation with verilog v2k you can use $display to print a message:

always @* begin
   $display("----- Starting verification of programmed SNN parameters");
   if(snn_0.spi_slave_0.SPI_GATE_ACTIVITY !=  1'b1) 
      $display("fatal: SPI_GATE_ACTIVITY parameter not correct.");
   ...
end

answered Aug 23, 2020 at 18:29

Serge

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4 Comments

dreamer1375 Over a year ago

you mean the line "else $fatal(0, "SPI_OPEN_LOOP parameter not correct.");" is replaceable with: "$display("fatal: SPI_GATE_ACTIVITY parameter not correct.");"??? they do the same thing?

Serge Over a year ago

Assertion prints a message about failure. So does $dislpay in this case. Depending on implementation, assertion might provide more information about failing expression and location of the assertion. You can use ` __ LINE __ or ` __ FILE __ print location of your $display.

Light Over a year ago

The first $display is not periodically executed.

Serge Over a year ago

right, it will only execute when there is any change in any of signals that you check. This is how the always block works.

dreamer1375 · Accepted Answer · 2020-08-24 07:58:46Z

1

To sum it up, Xilinx ISE does not support SystemVerilog, so we can not use assertion. To run this testbench I have to use Xilinx Vivado. Another way is to implement some function equivalent to assertion in verilog. Look at these answers at "Assert statement in Verilog"

answered Aug 24, 2020 at 7:58

dreamer1375

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