VHDL: Is it possible to define a generic type with records?

Question

I am trying to define a complex type (i.e, a type that consists of both a real and imaginary part) and am trying to find out a way to make it generic.

This my current static code:

  type complex_vector is record
    Re : signed(15 downto 0);
    Im : signed(15 downto 0);
  end record;

Now I wonder whether there is a way to make this generic, in in other word something like:

  type complex_vector (Generic: Integer := WIDTH) is record
    Re : signed(WIDTH downto 0);
    Im : signed(WIDTH downto 0);
  end record;

I tried to google for a solution as well as going through my books, but I cannot find any solution. Is there really none? Without records it is possible to wright something like this:

type blaaa is array (NATURAL range <>) of STD_LOGIC;

Thanks for any input

EDIT:

Or could I do something like the following?

type complex_primitives is (re, im);
type complex_vector is array (re to im) of signed(natural range <>);

The compiler complains though..

That seems very unusual to define a complex type using integers for the real and imaginary parts. — mark4o
– mark4o, Commented Jun 15, 2011 at 16:31
@mark4o: If you are doing signal processing in gates, that is normal. Until recently FPGAs didn't have floating point. — Brian Carlton
– Brian Carlton, Commented Jun 17, 2011 at 15:37

Josh · Accepted Answer · 2011-06-16 01:36:38Z

9

The following is legal syntax in VHDL-2008:

type complex is record
  re : signed ;  -- Note that this is unconstrained
  im : signed ;
end record ;

signal my_complex_signal : complex (re(7 downto 0), im(7 downto 0)) ;

IMPORTANT NOTE This example makes use of records with unconstrained arrays. Support for VHDL-2008 at this point is hit-and-miss. Some tools support many of VHDL-2008 features, but many do not yet fully support all new features.

To read about VHDL-2008 and the new features, see this presentation which is a good summary on the subject.

answered Jun 16, 2011 at 1:36

Josh

3,65529 silver badges37 bronze badges

Sign up to request clarification or add additional context in comments.

2 Comments

Andreas Sjöström Over a year ago

So if you don't use VHDL-2008 it is not possible? :-( Thanks anyway! If I would synthesize it with Xilinx ISE, you think it would be supported?

Josh Over a year ago

Unfortunately I don't believe Xilinx XST (built in synthesis tool) supports VHDL-2008 to date. Some other tools such as Synplify have limited support for VHDL-2008. Right now VHDL-2008 is a mine field because your simulator might support some features, but your synthesis tool might not (and vice versa).

Chiggs · Accepted Answer · 2011-06-16 15:57:21Z

7

Until VHDL-2008 is supported (don't hold your breath!) there are is a sub-optimal fudge...

Create the different sized records you want in multiple packages of the same name and then optionally compile in the package defining the width you want to use.

-- complex_vector_16.vhd
package types is
  type complex_vector is record
    Re : signed(15 downto 0);
    Im : signed(15 downto 0);
  end record;
end;

-- complex_vector_32.vhd
package types is
  type complex_vector is record
    Re : signed(31 downto 0);
    Im : signed(31 downto 0);
  end record;
end;


library complex.types
use complex.types.complex_vector;

The severe limitation of this method is that you can only support a single form of complex_vector in the design, but on the plus side you don't have to worry about tool support!

It would be useful to raise a support/enhancement request with every vendor in your toolchain regarding your use case. The more they get bugged the sooner VHDL-2008 will be supported.

edited Jun 16, 2011 at 15:57

answered Jun 16, 2011 at 15:51

Chiggs

2,86424 silver badges32 bronze badges

2 Comments

Andreas Sjöström Over a year ago

I will raise it with the vendors :-). Thanks for the solution. That is exactly how I have implemented it.

user1155120 Over a year ago

You could also define all these with unique names in the same package and use a non-object alias in an entity_declarative_item, block_declarative_item, subprogram_declarative_item, package_declarative_item, package_body_declarative_item, protected_type_body_declarative_item or process_declarative_item. With -2008 support there's also a generic type.

Collectives™ on Stack Overflow

VHDL: Is it possible to define a generic type with records?

2 Answers 2

2 Comments

2 Comments

Your Answer

Linked

Hot Network Questions

Collectives™ on Stack Overflow

2 Answers 2

2 Comments

2 Comments

Your Answer

Sign up or log in

Post as a guest

Linked

Related