Automatically constrain string size using initialization in VHDL

Question

I'm working with VHDL, and I'm wondering if there is any way to constrain the string size when declaring it, using initialization. For example, we declare a string as follow:

variable sequence : string(1 to 20) := "AGTAACCAATTCGCATTCGC";

I would like to know if there is any way to do something like:

variable sequence : string := "AGTAACCAATTCGCATTCGC";

Of course, second line isn't valid, because interpreter says:

[VRFC 10-1547] variable cannot be unconstrained

Once VHDL 2019 gets some support, then the second way will be valid. — Tricky
– Tricky, Commented Oct 20, 2020 at 6:44

Matthew · Accepted Answer · 2020-10-20 06:38:11Z

4

Constants don't have to be constrained, so you could do this:

constant Csequence : string := "AGTAACCAATTCGCATTCGC";
variable Vsequence : string(Csequence'range) := Csequence;

https://www.edaplayground.com/x/r3wK

entity E is
end entity E;

architecture A of E is
begin
  process
    constant Csequence : string := "AGTAACCAATTCGCATTCGC";
    variable Vsequence : string(Csequence'range) := Csequence;
  begin
  wait;
  end process;
  
end architecture A;

answered Oct 20, 2020 at 6:38

Matthew

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3 Comments

class_OpenGL Over a year ago

That's a nice trick! Thank you. I hope VHDL interpreters updates to 2019. Until that, I'll use your trick.

user1155120 Over a year ago

There's also a function to return the length of the string literal. variable sequence: string (1 to strlen("AGTAACCAATTCGCATTCGC")) := "AGTAACCAATTCGCATTCGC";

user1155120 Over a year ago

You can use the function to produce a range stored in a subtype declaration:

subtype gac is string (1 to strlen("AGTAACCAATTCGCATTCGC")); variable sequence: string (gac'range) := "AGTAACCAATTCGCATTCGC";

(This counts on the string literal being static).

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