Implementing combinational lock in verilog

Question

Problem Statement:

Design and implement a control unit for a digital lock. The digital lock has the passcode “1010”. The code should be entered via 2 Push Buttons: one button for entering 1’s (B1) and another for entering 0’s (B0). Use a third push button (Reset) to add reset functionality. Based on the entered code, glow an LED for the following outputs

LED_0 will glow indicating PASS, if the entered 4-digit binary code is correct

LED_1 will glow indicating FAIL, if the entered 4-digit binary code is incorrect

We need to make sure output is given only after all four inputs are taken.

Error: My coded module won't ever show a pass or fail output.

FSM State diagram to be implemented

module lock_FSM(
    input B0,
    input B1,
    input Reset,
    input Clk,
    output reg PASS,
    output reg FAIL
    );
    reg [3:0] present_state, next_state;
    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100;
    parameter E1 = 4'b0101, E2 = 4'b0110, E3 = 4'b0111, E4 = 4'b1000;
    
    //State register
    always @(posedge Clk, posedge Reset)
    begin    
    if(Reset == 1)
        present_state = S0;     
    end

    always @(posedge B0, posedge B1)
    begin
        present_state = next_state;
    end
    
    //Input block
    always @ (present_state, B0, B1)
    begin
    if(B0 == 0 && B1 == 0)
    next_state = present_state;
    else
    case (present_state)
    S0 : next_state = B1 ? S1 : E1;
    S1 : next_state = B0 ? S2 : E2;
    S2 : next_state = B1 ? S3 : E3;
    S3 : next_state = B0 ? S4 : E4;
    E1 : next_state = E2;
    E2 : next_state = E3;
    E3 : next_state = E4;    
    endcase
    end
    
    //Output
    always@(present_state)
    begin
    case(present_state)
    S4: begin PASS = 1; FAIL = 0; end
    E4: begin PASS = 0; FAIL = 1; end
    default : begin PASS = 0; FAIL = 0; end
    endcase
    end
endmodule

The output should have been PASS = 1 after 4th posedge in (B0 or B1) and stayed there until Reset is pressed.

I need to update the states only when one of B0 or B1 is pressed (as B1 and B0 are push buttons).

toolic · Accepted Answer · 2021-09-28 21:36:58Z

There is a problem with how you coded your state register. All assignments to a signal should be made within a single always block, not from 2 blocks. Change:

always @(posedge Clk, posedge Reset)
begin    
if(Reset == 1)
    present_state = S0;     
end

always @(posedge B0, posedge B1)
begin
    present_state = next_state;
end

to:

always @(posedge Clk, posedge Reset) begin    
    if (Reset == 1) begin
        present_state <= S0;     
    end else begin        
        present_state <= next_state;
    end
end

In a typical FSM, updating the present state should be unconditional (not dependent upon signals like B0). You should account for those conditions in your next_state logic. Also, good coding practices recommend nonblocking (<=) assignments in sequential always blocks.

Another issue is that you have no way to exit the E4 state (aside from an asynchronous reset). Perhaps you should add a case to your case statement for that. Also, since you declared only 9 of the possible 16 states, the convention is to use a default statement to handle the undefined states.

Collectives™ on Stack Overflow

Implementing combinational lock in verilog

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related