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I'm trying to do some projects on Verilog, and I have a problem with constant index errors.

integer k=32;
reg[k-1:0] inputs;

In this code, the Verilog compiler gives me this message:

Expected a constant as index error in Verilog

I must use integer k in this project. How can I solve this problem?

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1 Answer 1

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integer is a variable type. As the error message states, you need a constant type, such as parameter:

parameter k=32;
reg[k-1:0] inputs;
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