Negating a sequence in SystemVerilog assertions

Question

I have a reasonably basic SVA question, but I'm not sure what the trick is for getting somewhere. I'm trying to say that if A is true for 32 cycles, then B should become true at some point. Equivalently, I could say A && !B is not allowed to be true for 32 cycles.

Is there a way to encode this as a SystemVerilog assertion? I'm in an FPV context, so it would also be really nice to avoid encoding "not xyz" as xyz |-> 0 (to avoid the tool reporting a hole in the coverage).

Rupert Swarbrick · Accepted Answer · 2024-04-11 15:54:29Z

0

Well, that was easier than I feared! It turns out that you can negate properties with a not operator. So the example above turns into something like not ((A && !B) [*32]).

For the original context for the question, see OpenTitan PR #22528.

answered Apr 11, 2024 at 15:54

Rupert Swarbrick

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