When compiling my vhdl code is get a conversion error at line 28.
Error:
Error (10305): VHDL Type Conversion error at registers.vhd(28): cannot convert type " universal_integer" to type "MemoryArray"
Here is the code I am trying to compile:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity registers is
port( load : in std_logic; -- 1-bit input
WriteAddr : in std_logic_vector(1 downto 0); -- 2 bit write address
Memin : in std_logic_vector(5 downto 0); -- 6 bit input data
clk : in std_logic; -- clock
Memout : out std_logic_vector(5 downto 0)); -- 6 bit output data
end registers;
architecture arch of registers is
type MemoryArray is array(0 to 3) of STD_LOGIC_VECTOR(5 downto 0); --array of size 4, each index holds 6 bit values
signal Memory : MemoryArray := (others => (others => '0'));
begin
process(clk)
begin
if rising_edge(clk) then
if (load = '1') then
case WriteAddr is
when "00" =>
MemoryArray(0) <= Memin;
when "01" =>
MemoryArray(1) <= Memin;
when "10" =>
MemoryArray(2) <= Memin;
when "11" =>
MemoryArray(3) <= Memin;
end case;
end if;
end if;
end process;
process(WriteAddr)
begin
case WriteAddr is
when "00" =>
Memout <= Memory(0);
when "01" =>
Memout <= Memory(1);
when "10" =>
Memout <= Memory(2);
when others =>
Memout <= Memory(3);
end case;
end process;
end arch;
I am essentially creating a LUT that I can get the values at each index and change the values at each index with the given Memin value.
