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I have an exercise that asks me to calculate the bandwidth of a CPU with split cache memory for instructions and data. I have the references per second, miss and hit ratio, and the block size for both memories. The formula i'm using for this exercise is:

Main memory Bandwidth formula

My question is, since I have a split memory, do I need to calculate the bandwidth for each one and add them together to get the final result? Also, does each of the memory do read and write? My doubt arises since I don't know why would instruction memory do writing, in that case, the formula for the instruction memory would be simplified right?

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  • You have to write to instruction memory when loading programs into it. You don't usually write to it while the program is running. Commented Jan 17 at 0:31
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    @Barmar: And with split cache in front of unified memory (aka Modified Harvard), instruction cache can be truly read-only, only populated by read misses. Read misses from I-cache compete for memory bandwidth with data load misses and write-backs. (Or contribute to the total if you're calculating it from access rate and miss rate.) Commented Jan 17 at 0:41
  • @PeterCordes Right. I was thinking of I and D as separate memories, but they're just separate data paths. When you load the program, you use the data path, then switch to the instruction path when executing. The I path shouldn't need a write operation. Commented Jan 17 at 0:46
  • @Barmar: Right, yeah in mainstream CPUs. Or you just have the disk controller DMA pages of file data into DRAM, never touching D-cache. (Unless you're doing disk encryption, transparent decompression, or block checksums... Or if you're generating machine code on the fly with JIT compiling.) There are some true Harvard microcontrollers where the program is in flash or other NVM, and data is in RAM. Some like AVR allow data load/store from "program" memory, like AVR lpm and spm, so you can have static constant data there. Or just ARM with separate external buses. Commented Jan 17 at 0:51
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