35 questions
1
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1
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104
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How are MMIO requests routed in CPU microarchitecture — cache-bypass on same path or a separate bus/port?
Short background: MMIO regions are typically mapped as uncachable / device memory, so CPU must not treat device registers like normal cacheable DRAM. I’m asking about the microarchitecture routing and ...
- 13
1
vote
1
answer
134
views
Accessing one byte of a multi-byte volatile register
Suppose we have a pointer p, of type volatile int*. Assume that this is a currently valid pointer, i.e., reading from *p performs an implementation-defined operation, and is not UB.
What can happen if ...
- 123k
0
votes
0
answers
129
views
Want to know the PCIe MMIO request payload unit size
I am searching for the unit size of the MMIO request when sending to the PCIe device BAR region from CPU.
I used this code. In the below code, you can see that the MMIO accessing code between the &...
0
votes
0
answers
123
views
RISC-V softcore GPIO (memory mapped) sends the first value and fails later
I have a RISC-V softcore based SoC (PICO-SoC) and I have implemented memory (32'h 00000090) mapped output port to send a set of values. The set up is running on PYNQ FPGA board. The softcore provides ...
- 29
2
votes
0
answers
1k
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what is difference between readl() and *
In linux kernel.
I get a reg [phy_addr], and do ioremap(), get [vir_addr],
when i want to get val of this reg, What's the difference between readl() and *?
u32 value;
phys_addr_t phy_addr = ...
1
vote
0
answers
48
views
Verification of MIPS Assembly Code for Memory-Mapped I/O
I am seeking assistance from the community to verify the correctness of a MIPS assembly code that I have written to translate a C code involving memory-mapped I/O operations. The C code includes the ...
- 129
0
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0
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59
views
I can no longer modify my files! What happened?
I was working on a vuejs project when all of a sudden some files become immutable. In the browser, they appear with a double marked (mapped).
I don't know what it is . So, what I can do to revert this ...
- 553
2
votes
0
answers
39
views
Can character devices be mapped to memory?
Why we can map block device files to memory but not character files? I know block devices can be mapped to memory, but character devices can't. Why is it like that? I have no idea. Maybe someone can ...
- 27
0
votes
0
answers
54
views
Facing too much Insufficient Memory exception while working with memory mapped-IO files
I am trying to create memory-mapped IO files for having sized ( 1-100 GB ) files. These files will contain random data that will be generated during the process.
So, I am trying to generate partitions ...
- 2,900
3
votes
0
answers
252
views
How can I access memory-mapped GPIO registers with golang on Windows?
I am working with a piece of harware, that addresses LEDs through GPIOs accessible only through memory-mapped IO (mmio registers).
On Linux, I managed to set the values pretty simple, by opening the ...
0
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0
answers
764
views
How can I map device's IO memory to userspace using `mmap()`?
I'm browsing through LDD3 and I have difficulty understanding a chapter about mmap().
Here is a code snipped from the book:
static int simple_remap_mmap(struct file *file, struct vm_area_struct *vma)
{...
- 2,261
0
votes
0
answers
661
views
"busybox devmem <address>" returns 0xffffffff for all addresses on Nvidia Jetson Orin Nano, throws kernel error
I'm trying to configure a GPIO pin on an SoC running Linux (Jetson Orin Nano), but there's no API provided to set things like pull resistors, so we have to look up the physical addresses of the ...
- 1,609
2
votes
1
answer
4k
views
How to access MMIO registers in Linux kernel with `ioremap()`?
I am working on an embedded Linux system (kernel v5.10.24). And I want to access registers in the SoC which are MMIO based.
So I worked a test module to access them, as follows,
#include <linux/...
- 1,307
2
votes
0
answers
493
views
Poor MMIO performance with non-temporal loads on Intel Xeon
I'm seeing poor memory (WC) read performance with the vmovntdqa non-temporal load
instruction on Intel Xeon E-2224 systems, but excellent performance on AMD
EPYC 3151 systems. Why such a huge ...
- 91
1
vote
0
answers
616
views
any known issue with ioread64() / iowrite64() on a PCIe bus?
I have a similar issue mentioned here but with a different behavior.
We have an FPGA (from Altera) acts as a 32KB memory on a PCIe bus of IMX8M-Plus CPU (ARM Cortex-A53).
I wrote a simple driver to ...
- 1,794
0
votes
1
answer
164
views
TM4321GH6PM - why is GPIODATA register initializing itself and how to read and write to it properly?
Context: I am following a Embedded Systems course that uses the TM4C321GHP6M microcontroller. The IDE being used is the uvision ide by keil. The purpose of the program I am running is to turn on an on-...
- 23
3
votes
1
answer
796
views
Better way to write a few MMIO register bits in RISC-V assembly?
To configure UART tx, water mark (0 to 7) has to be written
on memory mapped tx control register on bit position [18:16].
My RISC-V assembly function first reads the present control register value, ...
- 1,135
1
vote
1
answer
123
views
polling through mips doesnt work after the first time you run the program (MIPS)
i made a polling sequence and when i first open the program (on QtSpim) it polls perfectly, when i reinitialize and reload the program a second time it just falls through and doesnt poll at all and ...
- 11
0
votes
1
answer
1k
views
What is "Polling" in MIPS and how exactly do you "Poll" in Memory Mapped I/O
having trouble warpping my head around this topic, simple internet searches only show Interrupt Handling so im assuming its a type of interrupt? sorry if im being dense.
- 1
0
votes
1
answer
523
views
Embedded software and device registers
This one is going to be short. I have a question regarding manipulations on device registers. As maybe you guys know, device registers addresses are determined by hardware so in order to write code ...
4
votes
1
answer
1k
views
Is there an elegant way of parsing a byte buffer of dynamic length into a struct?
Background
As sketched up here https://godbolt.org/z/xaf95qWee (mostly same as code below), I am consuming a library that offers a shared memory ressource in form of a memory-mapped file.
For ...
- 108
2
votes
2
answers
2k
views
How to put a variable at a specific memory location in SDCC
For low-level programming, sometimes it's necessary to say, at a given memory location, this is where my address is. For this post, the example is the PIR1 register in the PIC16F886 and related ...
- 1,266
0
votes
0
answers
88
views
Keeping memory mapped files from growing too large
I'm wanting to use memory-mapped IO to establish communications between two applications of mine (primarily to avoid the problem of sockets tending to leak to other computers on the network). However, ...
- 134
1
vote
2
answers
288
views
Memory-mapped C++ objects non hardware members
I am developing a driver for a piece of memory mapped hardware using C++ and I defined a class that represents this device. It looks something like this:
class device
{
method1();
method2();
private:
...
- 113
1
vote
2
answers
2k
views
What exactly is memory mapped io and port based io
Well I have some confusions about memory mapped io and port based io. Questions are:-
In port based io if I write to a port will it affect the corresponding memory address or not and vise versa.
Does ...
- 35
2
votes
3
answers
228
views
How to have a constexpr pointer to CMSIS defined hardware peripheral?
I want to use constexpr instead of #defines wherever possible, for type safety and namespace features.
Unfortunately, I get this error: 'reinterpret_cast<SPI_TypeDef*>(1073756160)' is not a ...
- 7,513
0
votes
1
answer
172
views
Detect unclean filesystem shutdown
I have a project where we manipulate large amounts of cached data using memory mapped files. We use Windows 10, NTFS and .NET.
When the user starts the application, we detect if the previous program ...
- 622
0
votes
0
answers
223
views
Where can I find I/O address range of BIOS?
I have been reading this chipset datasheet for a while, looking for the BIOS I/O address range, but I haven't found it.
Where can I find the BIOS address range? Is it on this datashhet or should I ...
- 391
0
votes
0
answers
785
views
Why do I get a segfault when writing to a file using mmap?
I recently learned from a YouTube video that we can read from or write to files by mapping them into memory. The video showed how read some contents from a text file and print them out and also change ...
user14526699
1
vote
2
answers
2k
views
reading Memory-Mapped IO registers How to (from datasheet) and using them in mmap
I have intel system with Ethernet controller: Intel Corporation 82579LM Gigabit Network Connection (Lewisville) (rev 04). I have downloaded the datasheet like datasheet for Intel ® 82579 Gigabit ...
- 4,440
0
votes
0
answers
2k
views
Writing to read only address with kernel driver c++
Im trying to write memory to a user mode process with kernel driver,
the current address im trying to write memory for is read only, I want to write 4 bytes to the current address,
the thing is if i ...
- 17
0
votes
1
answer
2k
views
c++ memory write bytes to address with Windows kernel driver
so I will explain what im trying to do and i wanna understand why its not working for me,
I found an Address from CE : which is: 0x04013118 with value an array of bytes: DC 04 00 00 04 02 00 00
What ...
- 17
1
vote
1
answer
2k
views
What is non-idempotent memory-mapped I/O meaning?
In RISCV privileged spec page 75 mention a term "non-idempotent memory-mapped I/O". What is non-idempotent memory-mapped I/O? Is it about non side effect?What is design concern about non-idempotent ...
- 125
0
votes
0
answers
1k
views
MIPS: Reading and displaying a character using polling
I am trying to display a single character in Mars MIPS (then eventually an entire string, but I am working on a single character for now).
.data
.text
main:
jal emitchar
jal LOOP
jal ...
5
votes
3
answers
727
views
Why are memory locations also called registers?
In embedded systems and systems programming, the term register is used to refer to
a CPU register inside the micro-controller, e.g. R1, R2, PC in ARM micro-controllers, and
certain 'special' locations ...
- 4,470