Is it fine to have different number of input/output port in module and module instant in verilog?

Question

For example if i am going to model T flip flop using D flip flop. I am not writing the whole code of T flip flop as here it is not related to my query.

module T_ff(q,clk,clear);            
//...............   
//Instantiate the D flip flop          
D_ff dff(q,~q,clk,clear);            
endmodule  


// edge triggered D flip flop             
module D_ff(q,qbar,d,clk,clear);             
//..............                                    
endmodule

The number of input/output ports are different in Instantiate of D flip flop (define inside the T flip flop) and in module of D flip flop. Is it fine? Can it result in error?

MarkU · Accepted Answer · 2014-05-10 06:42:01Z

When using Port Order connections, the ports are connected in the order declared by the module, and any unused ports are left unconnected (Z).

Instantiating by Port Name connections helps avoid this kind of problem.

Your code is interpreted as this:

D_ff dff_instance (  
        .q     ( q     ), // first port
        .qbar  ( ~q    ), // second port
        .d     ( clk   ), // third port
        .clk   ( clear ), // fourth port
        .clear ( 1'bZ  )  // fitfh port has no connection
    );

Clearly what you intended was this:

D_ff dff_instance (  
        .q     ( q     ),
        .qbar  (       ),  // unconnected output
        .d     ( ~q    ),  // toggle by driving dff_instance.d input from ~q
        .clk   ( clk   ),
        .clear ( clear )
    );

If you are using an older verilog compiler that does not support Port Name connections, skip the unused port by two commas:

D_ff dff_instance ( q, , ~q , clk, clear); // qbar output port is unconnected

The Port Name connection style does require more typing, but makes the code easier for a person to read and understand, and more robust against connection errors.

Just at a curiosity, what older verilog compiler does not support port name connections? It would have to be before the first IEEE verilog standard or it will be non-compliant with IEEE 1364-1995 § 12.3.4 Connecting module ports by name. — Greg
– Greg, Commented May 12, 2014 at 17:10
You're right, any modern verilog compiler should accept connecting ports by name. Sometimes student example code uses port order connections, which isn't as clear in my opinion. As soon as I learned how to enable Xilinx ISE 12 to use Verilog-2001, I started coding this way and haven't looked back. — MarkU
– MarkU, Commented May 13, 2014 at 3:25

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