I have written this code in system verilog to generate fifty 12-bit random numbers and write them to a file.
How can I generate the random numbers in octal instead of decimal?
Also, how can I make the numbers display on different lines? Currently, my numbers are being displayed one after the other.
module stimulus_gen();
class stim_gen;
rand bit [11:0] addr;
endclass
integer file;
stim_gen obj;
initial begin
file = $fopen("input.txt", "w");
while (!$feof(file))
begin
for (int i=0; i<50; i++)
begin
obj = new();
assert(obj.randomize())
else $fatal(0, "stim_gen::randomize failed");
//transmit(obj);
$fwrite(file, obj);
end
end
$fclose(file);
end
endmodule
while (!$feof(file))will be an infinite loop. Also$fwrite(file, obj);will write the memory address of the object, not the objectsaddr. \$\endgroup\$ifstatement instead of using anassert. This keeps the assertion coverage reports specific to the verification of your design, not for debugging your testbench. Also, some tools will not execute the expression inside an immediate assertion of you globally disable assertions. Sometime people do that for performance when debugging. \$\endgroup\$