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I'm programming FPGA boards (Artix 7 to be exact) and I recently noticed that, in order to be synthesized into block RAM, an array of storage must have synchronous reading, otherwise it will only be synthesized into a register file.

Example of async read (can't become block RAM):

always @(*)
    rd_data <= mem[addr];

Example of sync read (may become block RAM if other conditions are plausible):

always @(posedge clk)
    rd_data <= mem[addr];

Why can't a block of storage with asynchronous read be a block RAM on Xilinx FPGA?

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  • \$\begingroup\$ There are synchronous and asynchronous RAMs. In computer systems they are called high density and low density. \$\endgroup\$ Commented May 13, 2020 at 18:43

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To put it bluntly, because that is how Xilinx have implemented block RAM in the 7 Series FPGAs.

The data sheet is here:

https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

This in extract from the datasheets showing how the ports work:

enter image description here

As there is no asynchronous read block RAM in Series 7 FPGAs, when you write an async block RAM it will be synthesised as logic.

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  • \$\begingroup\$ This is not really an answer to the question asked - all you are doing is confirming the fact stated as the premise of the question. But the question asked, was "why" \$\endgroup\$ Commented May 28, 2020 at 19:21
  • \$\begingroup\$ @ChrisStratton I disagree. The question asks about Synthesis and gives code examples of async and sync block rams and asks why the async isn't synthesised as ram. I believe I have answered why that is. \$\endgroup\$ Commented May 29, 2020 at 9:28
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Generally, FPGA designs are synchronous, so that is the type of RAM which FPGA vendors implement. It allows for higher clock frequencies than asynchronous RAMs can support. There are however FPGAs out there which have asynchronous read RAM blocks. The Smartfusion2 series from Microchip for example.

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