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Consider instead more specific tags, e.g., dram, sram, flash

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I have a New Holland W130b loader with a main battery disconnect switch. The switch kills ground to the system. The stereo I removed was analog, I wanted digital with bluetooth and I can not see the ...
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I have this SOM module. I initially planned to boot the SOM module from a NAND Flash IC that uses a parallel interface (requiring address, clock, enable, and data signals). According to the datasheet, ...
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I am using a Microchip SAMA5D27 Wireless System-On-Module 1 (ATSAMA5D27-WLSOM1) MPU SOM Module with a Micron MT29F4G08ABADAWP-IT:D NAND Flash device for storing the boot image. I will also use a 4-bit ...
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While shopping for 32 GiByte DDR5 ECC UDIMMs, I found pictures with 20 identical DRAM ICs, where I was expecting 18, because that's been the usual number for large DDR/DDR2/DDR3/DDR4 ECC UDIMMs, and I ...
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I’m working on a DDR4 PCB layout and want to confirm the allowed rules for bit swapping, byte lane swapping, and nibble swapping, especially when ECC or CRC is enabled. From what I understand so far: ...
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I'm looking at this RAM: https://gr.mouser.com/ProductDetail/Ramxeed/MB85R4M2TFN-G-JAE2?qs=sGAEpiMZZMs6Aik9Fp479ij4Y1Ujk4wm%252B7sI6f6xMBM%3D How big diameter are the pins of this RAM? Can I stick it ...
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I am in searching of better 256Mbit replacement of existing 128Mbit QSPI NOR flash memory chip on HW platform I work on and have met very interesting feature among the others which is Memory ...
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I recently completed fly-by routing for 2 x DDR3 and a Zynq 7000 chip by studying their app notes or general notes on how to do fly-by routing. Now that I finished the routing then I started having ...
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When you're programming for performance, it's important to reduce the amount of copies, because copying data is (relatively) slow. But why does it have to be that way? In my naïve conception, data is ...
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I am using a Micron NOR Flash Chip (MT25QL128ABA) along with a Zynq-7020 FPGA. I have implemented a QSPI driver in Verilog, which successfully communicates with the Flash behavioral Verilog model in ...
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I'm implementing a DDR3 controller using Xilinx MIG on a Spartan-6 XC6SLX16-2FTG256 FPGA. The DDR3 memory I'm using is MT41J128M16. The issue is that, during write operations, the upper byte (DQ[15:8])...
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In a solution to an exercise in my notes for a Computer Architecture course, it is stated that each memory address has a length of 64 bits, and I do not understand why. The problem statement is as ...
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Suppose i have two numbers n1 & n2, one in bank 0 and the other in bank 2, i want to do a sum operation on them using the indirect addressing approach, here is the code from my lecture which is ...
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This question is about how multiple DDR5 DIMMs in the same memory channel are wired to the processor. This is mostly an electrical engineering question, and the goal to answer this question: Will re-...
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In the Digital Design and Computer Architecture RISC-V Edition page 442, a pipelined CPU is designed with separate instruction and data memories, as shown in the figure below. However, this picture ...
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How does nMOSFET conduct both ways in a DRAM cell? Doesnt the constrain of always keeping the source lower than the drain in potential restrict current flow only one way? I know a 4 terminal nMOS is ...
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I am looking to write a page program for this W25Q64FV Flash component. I want to use a full sector of 256-bytes. I have learned ...
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In the Page Program section of the docs for the AT25SF0818 Flash device, it says it is first necessary to erase a specified section of memory before writing to it. ...
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What type of memory is used on the PCB of 2.5" and 3.5" HDDs to store BIOS/firmware and S.M.A.R.T files? How many years will these chips retain data in my room temperature of 33-36C?
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Well, I'm developing a system for reading sensors and sending them to a server. I'm using a GSM LTE module to do this sending. At first it worked well, but after a while the system stopped sending ...
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I am trying to create a 2K flash memory region in which user defined const uint32_t will be stored. The project is built in Keil uVision. The microcontroller has 64K of flash memory. The idea is to ...
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ReRAM-based IMC techniques are promising for ML inference. Many research papers propose ReRAM IMC techniques for accelerating NN operations. However, they do not discuss the system integration of the ...
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I am looking at different CPU micro-architectures. Frequently, it happens that the ROM is supposed to contain only instruction data. See below for an example: In such design, how is the CPU supposed ...
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I am having some confusion regarding the stm32f446xx memory remap feature in the reference manual. The system configuration memory remap is used to change the memory at 0x00000000. I am having some ...
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I am confused in the bit banding of Cortex M4. I was going through the datasheet of STM32F446ZE and found in the memory map there was only written SRAM (112 kB aliased By bit-banding) What does that ...
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I have gotten very confused with how PCIe works. I read that PCIe is a memory mapped protocol. That is, if the GPU wants to write to the CPU it will access the DDR memory located on the motherboard ...
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How is a bit read from the core memory pictured below? I understand current through 1 and 1 vs 0 and 0 will change the torus magnets field setting a bit. I’m confused how this field is read back using ...
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I am planning to implement a remote firmware update for my MCU and seek recommendations on the necessary features for the MCU. Specifically, I would like to understand the requirements regarding ...
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I am debugging an issue I have on a legacy codebase that is running on an atxmega32c4u chip. I am writing single bytes to registers in PORTC, but the memory view is showing multiple bytes change. The ...
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I have an SRAM memory device GM76C88AL with this datasheet. The RAM was exposed to a radioactive beta source (~2MeV) for some time (about 2 hours). The source was just right above it (placed on it), ...
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In this buffer, we have two sections. Let's call these A and B. At one time we write into one but read from the other. So we write into A and read from B, or we write into B and read from A. We can ...
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I am doing a project with an STM32 chip. It needs to access megabytes of storage, but the chip can only access up to 32 Kilobytes of Flash memory. Is there a way to add more memory?
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I have a 1.8 V, 125 Msps ADC (ADS4125) with an output of 12-bit parallel LVDS or CMOS. The system is operating in bursts: the data is sampled for 8 - 30 us, with a 100 ms wait time in between. I need ...
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In a design, I have used a DDR4 SODIMM module, which has 64-bit data, thus 8 groups of data (DQ), DQS and DBI. However, I will only use the lower 32 bit on the module, thus have to handle the ...
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From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
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I'm providing assistance on a project that is encountering some interesting behavior on an SRAM memory device when environmental temperature goes up or when someone probes/touches lines associated ...
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This is a question for anyone with experience designing or with a deep knowledge of volatile memory in an ASIC. E.g. chip designers or silicon process engineers. We are using the ET1200 EtherCAT ASIC (...
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Ill be working with a board that has a STM32H743 on it, and I have a hard time reasoning about the f32 matrix-vector multiply performance I can expect of the m7 core. As I understand the core itself, ...
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From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
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The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same ...
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Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs. Given that synthesized hardware has static memory size, what's the ...
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I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this: But then, from Wikipedia article on memory ...
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Source: Page 31 ADXL355 MEMS' Datasheet. Source: Page 32 ADXL355 MEMS' Datasheet The above is some of ADXL355 Accelerometer Register map table. From that table, in the RESET column, there are their ...
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I am trying to implement a Y86 processor for my college assignment. This is my MemoryStage: ...
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Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the ...
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I'm having trouble writing to the status register of a SST25VF010A-33-4I-SAE 1Mbit SPI flash memory on a board I recently made. I'm using an STM32F401CBU6 to communicate with the memory. I can read ...
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We are in the process of figuring out which memory option would be the best for our needs. What are our requirements? Very simple Bandwidth: BW TB/s, say greater than 20TB/s Capacity: C TB, say 20TB ...
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I asked over a year ago (link) about why memory cells typically use paired inverters instead of paired buffers. The answer mentioned gain, "this is basically because it's hard to make non-...
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I've an ATmega328P. Register Summary Page 275 ATmega328P datasheet. The first address is the I/O address, and the second is the data memory address. I'm going to set all (D ports) Data Direction ...
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I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
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