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Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the part of word organized memory - where instead of a single bit being stored/accessed, an entire group of them is.

I have tried to contact the professor and come up with my own interpretations, but sadly I haven't gotten anywhere useful.

My point is that if stacking a 2D matrix is a solution to the problem, that would require us to include more input lines for accessing each matrix's bit, rendering the entire concept of reducing the number of input lines useless. Any ideas?

TLDR: I want to know how to read/write data in a word organized matrix addressable memory block.

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Yes, it's theoretically very elegant. But, how could this be achieved in reality?

It is very simple. I think you're trying to view it as something complicated, but it's a very basic solution.

Without going into too much detail of the circuitry, could you explain the main aspects of such a construction that would allow input/output of data in B sized cells?

Imagine that addressing hardware is expensive. In the times of core memory, it certainly was. So you wanted to have N row drivers, N column drivers, B sense/write amplifiers. The NxN matrices were called core planes, one bit per plane. B planes gave you B bits, all addressed at the same time.

You'd do the same with one-bit dynamic memory chips back in the 70s and 80s. The chips shared the address (muxed row/column), RAS and CAS signals (row address select and column address select respectively), but each chip had it own single bit data line. These were assembled to form 8, 16 or 32 bits as needed.

Below is the schematic of a memory system with following specifications:

  • 4 bits/word,
  • 16 words,
  • 2x2 bit planes,
  • demultiplexed addressing (row and column separate)

schematic

Within each plane (matrix), Rn are row addresses, and Cn are column addresses.

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  • \$\begingroup\$ Yes, in retrospect, I do feel that I was complicating it unnecessarily. Thanks. \$\endgroup\$ Commented Feb 19, 2024 at 12:50
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No, it doesn't render the concept useless. If you have N rows and N columns, you can address N2 distinct locations. By convention, the columns are the data lines. If you want to store B bits per location, you just need to either create B separate matrices, or multiply the number of columns in your matrix by B.

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  • \$\begingroup\$ Yes, it's theoretically very elegant. But, how could this be achieved in reality? Without going into too much detail of the circuitry, could you explain the main aspects of such a construction that would allow input/output of data in B sized cells? \$\endgroup\$ Commented Feb 18, 2024 at 13:57

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