Verilog netlist synthesis using assign vs always

Question

If you have some sort of Verilog implementation like:

module Example1 (input logic n);

   always @(*) begin
      a <= n;
      b <= n;
      c <= n;
   end

endmodule;

and another implementation like:

module Exmaple2 (input logic n);

   assign a = n;
   assign b = n;
   assign c = n;

endmodule;

Is the synthesis algorithm that Verilog runs going to create the same netlist for each circuit?

I am under the impression the synthesizer is able to simplify logic somehow, and in my understanding the above two examples are essentially identical.

toolic · Accepted Answer · 2023-02-14 19:07:40Z

Yes, your synthesis tool is likely to synthesize both code examples into the same logic. The same synthesis constructs can be represented using different coding styles; the same is true for simulation behavior.

Both styles you show are intended to represent combinational logic. In your 1st example, you use a procedural always block, where it is more customary to use blocking assignments (=) than nonblocking (<=):

module Example1 (input logic n);
   logic a, b, c;
   always @(*) begin
      a = n;
      b = n;
      c = n;
   end
endmodule

I realize you are only posting incomplete pseudocode, but the semicolon after endmodule is illegal syntax and should produce a compile error.

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