I'm trying to implement a Dadda tree multiplier in SystemVerilog using generate blocks. However, the algorithm I'm using to instantiate the logic requires arrays, and the genvar type does not seem to support arrays. In theory, I could use some external script to produce the required Verilog code, but that would be difficult to write and verify.
As part of the Dadda tree algorithm, I have to keep track of the heights of each partial sum column. For example, here is the first part of the algorithm:
logic [62:0][31:0] products[STAGES];
genvar i, j;
// Heights of each partial sum column
genvar colHeights[STAGES][63:0]; // syntax error
generate
// Record all the initial products
for (i = 0; i < 32; i++) begin : a_loop
for (j = 0; j < 32; j++) begin : b_loop
assign products[0][i+j][colHeights[0][i+j]] = a[i] & b[j];
colHeights[0][i+j] = colHeights[0][i+j] + 1;
end
end
// ...
endgenerate
colHeights is supposed to be a multidimensional array, but my compiler does not seem to recognize that.
Is there a way to create arrays which can be read from and written to during module instantiation? If not, is there another way I can instantiate modules based on the results of an algorithm like this?
genvaris just a loop iterator that gets unrolled into a constant at compilation. It is not a variable. You need to explain what kind of array you want; an array of wires, variables, or module instantiations. It might help to show a piece of code without usinggeneratethat manually describes what you want to do. \$\endgroup\$