What's the difference between a += 1 and a = a+1 in Verilog?
always_comb begin
a = '0;
a += 1;
end
always_comb begin
a= '0;
a = a+1;
end
Is the 2nd case a combinational loop?
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2 Answers
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a+=1 is just a short-hand for a=a+1. They both are equivalent.
There is no combinational loop in both cases.
a will be simply driven 1 in both cases. Synthesiser usually flags this as warning or info.
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These are equivalent assignment statements in SystemVerilog—there is absolutely no difference. And the two always_comb blocks do absolutely nothing as they have no sensitivity to any variables. In fact, some tools may generate warnings or errors stating that the blocks do not represent combinational logic.
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1\$\begingroup\$ The
always_combwill run once per IEEE1800-2017 § 9.2.2.2.2 always_comb compared to always @* "always_combautomatically executes once at time zero, whereasalways @*waits until a change occurs on a signal in the inferred sensitivity list." \$\endgroup\$Greg– Greg2019-12-03 16:30:22 +00:00Commented Dec 3, 2019 at 16:30 -
\$\begingroup\$ Yes, that's true for simulation. Not sure how synthesis tools treat time 0 behavior \$\endgroup\$dave_59– dave_592019-12-03 16:32:58 +00:00Commented Dec 3, 2019 at 16:32
+=with=+because those expressions are different. \$\endgroup\$