Why does passing the subrange of a bitvector to a module in Verilog produce an unexpected result?

Question

To better understand what it is that I'm asking about, please compare "Code A" to "Code B" below. Code B is more compact, but unfortunately does not produce what I would consider to be the "expected result" - which Code A does produce. I assume that the tools I'm using here do conform to the Verilog specification. I am trying to make sense of why this is the specified behavior. For example, does it make sense from some other perspective that I simply do not appreciate yet?

Note: In the waveforms, "speed" is the signal seen inside the MotorController module.

Code A

wire [9:0] motor0Speed;
wire [7:0] motor0SpeedDiv4;
assign motor0SpeedDiv4 = motor0Speed[9:2];
MotorController mc0(
    .clock(CLK0),
    .syncReset(syncReset),
    //.speed(motor0Speed[9:2]),
    .speed(motor0SpeedDiv4),

Code B

wire [9:0] motor0Speed;
MotorController mc0(
    .clock(CLK0),
    .syncReset(syncReset),
    .speed(motor0Speed[9:2]),  // <= This line of code is not working as I would expect!!!

If it's relevant, I'm simulating with:

Vivado v2023.2 (64-bit)
SW Build: 4029153 on Fri Oct 13 20:14:34 MDT 2023
IP Build: 4028589 on Sat Oct 14 00:45:43 MDT 2023
SharedData Build: 4025554 on Tue Oct 10 17:18:54 MDT 2023

Thanks, I wasn't blocked, but I was curious as to why this was the behavior. I think there's low probability of it being something else in my code in this case - I've been programming for decades and one develops a sense of when that might be the case. If it's a bug in the simulator, then if someone who maintains Vivado is ever assigned to it, I would be willing to help them figure out how to reproduce it. — phil1008
– phil1008, Commented Mar 26, 2024 at 18:59
I agree with you that it is likely a Vivado bug in this case because you are unlikely to be doing something odd inside your design code. Vivado seems buggier that most simulators. Do you have your own testbench code, or does Vivado drive your design inputs for you under the hood? I have very little experience with Vivado. — toolic
– toolic, Commented Mar 26, 2024 at 19:05
It's really just my code. A top.v file, testbench.sv file, and a pinmappings.xdc file with lots of "setproperty" commands in it. I'm programming a Spartan 7 FPGA. — phil1008
– phil1008, Commented Mar 27, 2024 at 1:54

toolic · Accepted Answer · 2024-03-24 09:30:39Z

Your expectation is correct. You should see the same simulation results given the 2 code snippets you have shown.

I can think of 2 possible explanations:

There is a bug in the version of the Vivado simulator you are using
The problem lies is the code you did not post.

Here is how I recommend that you debug the problem. The first thing to do is to create a minimal reproducible example of your code. This would include the testbench code that drives all the input signals (the clock, the reset, etc.).

It can be tricky to write robust Verilog code, and there are many subtle things that can go wrong.

Once you have a small complete code example, you can run a simulation on a different simulator. The EDA Playground site has several free simulators you can try.

This approach should help you isolate the issue.

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