I'll often use tools for designing switching regulators that will give me a recommended amount of bulk decoupling to handle some amount of step load to get a desired transient response and ripple. Additionally, most high power ICs I am trying to power will have their own guidelines for bulk decoupling. I imagine these requirements from the IC vendor are both conservative and are targeting the sort of step loads I am already designing my switching regulators around.
I am curious what the best practice would be for combining/handling these requirements. I can't imagine I would need both sets of decoupling capacitors recommended for source and load if the path is short and on the same board. I also want to minimize required board surface area. Should I just take which requirement desires more bulk capacitance and call that good? What sort of due diligence would give high confidence the power distribution network will function as intended? Is simulation/PDN analysis sufficient even if it maybe subverts what the IC requirements might state?