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Please help me understand how propagation delay changes depending upon the input bit pattern in a ripple-carry adder.

Take 2 cases:

  1. 100+011. here no carry generated or propagated
  2. 001+111. here carry is propagated throughout

As I understand it:

case 2 is a worst case, so max delay
case 1 is best case, so no delay caused by carry propagation

Adders are combinatorial, so I expect them to work with the given input.

Why is there this difference in delay?

I do not understand the concept of "gate waiting for previous carry". They would work instantly with whatever values they have at their inputs.

So how can there be difference in the speed?
For all bit patterns it should output at the same speed because the gates are the same. Right?

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  • \$\begingroup\$ "the gates are the same" all gates are equal, but sometimes, some are more equal (speed-power trade-off: in some "technologies" you get lower delay for more dissipation) \$\endgroup\$ Commented Oct 25 at 8:41

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The term "ripple-carry" says it all: the carry bits ripple up from one binary digit to the next.

Quite simplified, this is the principle: With your 3-bit adder, the final stable result will be output not earlier than after all 1-bit adders have propagated their result.

coz the gates are the same

Yes, that is correct, but your conclusion is not. If you determine the propagation delay of the complete 3-bit adder by adding all propagation delays of the gates in the critical path, you get the maximum propagation delay. This is roughly 3 times the propagation delay of a 1-bit adder.

However, values do not change for each combination of an old calculation and a new calculation. So the actual propagation delay of a new calculation depends on the old calculation.

In my explanation below I assumed 000 + 000 = 000 and 001 + 000 = 001, respectively, as the old calculation to demonstrate a short and a long propagation delay. \$t_{PD}\$ is the propagation delay of a 1-bit adder.

In the first case (100 + 011 = 111), all 1-bit adders output the result after \$1 \times t_{PD}\$, because they work in parallel and do not have to add any carry. So the complete result is stable after \$1 \times t_{PD}\$.

\$0 \times t_{PD}\$ \$1 \times t_{PD}\$ \$2 \times t_{PD}\$ \$3 \times t_{PD}\$
adder \$2 ^ 0\$ 0 (old value) 1 1 1
adder \$2 ^ 1\$ 0 (old value) 1 1 1
adder \$2 ^ 2\$ 0 (old value) 1 1 1

In the second case (001 + 111 = 000) the result needs \$3 \times t_{PD}\$, because each 1-bit adder can output the result only after the adder "before" has produced its output.

\$0 \times t_{PD}\$ \$1 \times t_{PD}\$ \$2 \times t_{PD}\$ \$3 \times t_{PD}\$
adder \$2 ^ 0\$ 1 (old value) 0 0 0
adder \$2 ^ 1\$ 0 (old value) 1 note 1 0 note 2 0
adder \$2 ^ 2\$ 0 (old value) 1 note 3 1 note 3 0 note 4

Note 1: adder \$2 ^ 0\$ did not yet output its carry.

Note 2: adder \$2 ^ 0\$ did output its carry.

Note 3: adder \$2 ^ 1\$ did not yet output its carry.

Note 4: adder \$2 ^ 1\$ did output its carry.

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  • \$\begingroup\$ @busybee is it the case that, the output is always available at same speed regardless of input bits, But in cases with propogation carry, those initial results are wrong and overwritten after the transient period? is it that the output if immediately fetched from the adder is wrong when having carry? but only corrected and stable after accounting for the extra delay? \$\endgroup\$ Commented Oct 26 at 5:13
  • \$\begingroup\$ @user339080 Yes, yes, and yes, as seen in the second table. One possible way to observe this is the implementation of the adder in a hardware description language like VHDL, complete with propagation delays, and the simulation of different calculations. You will see the "noise" at the output. \$\endgroup\$ Commented Oct 26 at 8:20

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