aboutsummaryrefslogtreecommitdiffstats
path: root/sys-utils/lscpu-arm.c
AgeCommit message (Collapse)AuthorFilesLines
5 dayslscpu: Add a few missing Arm CPU identifiersJonathan Thackray1-0/+5
2025-09-10lscpu: New Arm C1 partsJeremy Linton1-0/+4
Arm has announced the C1-Nano with a TRM here: https://developer.arm.com/documentation/107753/latest The C1-Pro with a TRM here: https://developer.arm.com/documentation/107771/latest The C1-Ultra with a TRM here: https://developer.arm.com/documentation/108014/latest The C1-Premium with a TRM here: https://developer.arm.com/documentation/109416/latest Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
2025-09-08lscpu: Add NVIDIA Olympus arm64 coreMatthew R. Ochs1-0/+1
Add an entry for NVIDIA Olympus arm64 core. Signed-off-by: Matthew R. Ochs <mochs@nvidia.com>
2025-03-06lscpu: New Arm part numbersJeremy Linton1-0/+4
Arm has announced the Cortex-A320 and published the TRM here: https://developer.arm.com/documentation/109551 The Cortex-A520AE with a TRM here: https://developer.arm.com/documentation/107726 The Cortex-A720AE with a TRM here: https://developer.arm.com/documentation/102828 The Neoverse-V3AE with a TRM here: https://developer.arm.com/documentation/101595 Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
2024-12-24lscpu: Add FUJITSU aarch64 MONAKA cpupartEmi, Kisanuki1-0/+1
Add an entry for FUJITSU aarch64 part MONAKA. Signed-off-by: Emi, Kisanuki <fj0570is@fujitsu.com>
2024-07-30lscpu: make code more readableKarel Zak1-3/+3
Signed-off-by: Karel Zak <kzak@redhat.com>
2024-07-30lscpu: Skip aarch64 decode path for rest of the architecturesPratik R. Sampat1-1/+36
lscpu behaves differently when run sudo vs non-sudo on AMD architectures. On sudo runs, it adds a BIOS model name and BIOS CPU family which it does not add for the latter. However since this parsing from the DMI is primarily catered to aarch64, for AMD platform the BIOS model name is printed out as follows "AMD XXX Processor *Unknown* CPU @ X.XGHz" due to the part number is not populated on the platform. The issue boils down to an unconditional call to arm_decode() which attempts to read the DMI path and populate the processor information such as processor version and part number which is set to Unknown on AMD CPUs. 81d6de9 (lscpu: remove the old code) changed the DMI path from /sys/firmware/dmi/entries/4-0/raw (non-existent) to /sys/firmware/dmi/tables/dmi (existent) which has brought this latent issue to light as DMI was starting to be parsed incorrectly. Therefore, do not perform aarch64 parsing for other architectures. Before ------ $ lscpu Vendor ID: AuthenticAMD Model name: AMD EPYC XXXX X-Core Processor CPU family: 26 $ sudo lscpu Vendor ID: AuthenticAMD BIOS Vendor ID: Advanced Micro Devices, Inc. Model name: AMD EPYC XXXX X-Core Processor BIOS Model name: AMD EPYC XXXX X-Core Processor Unknown CPU @ X.XGHz BIOS CPU family: 107 CPU family: 26 After ----- $ lscpu Vendor ID: AuthenticAMD Model name: AMD EPYC XXXX X-Core Processor CPU family: 26 $ sudo lscpu Vendor ID: AuthenticAMD Model name: AMD EPYC XXXX X-Core Processor CPU family: 26 Fixes: 81d6de9 ("lscpu: remove the old code") Co-developed-by: Karel Zak <kzak@redhat.com> Signed-off-by: Karel Zak <kzak@redhat.com> Signed-off-by: Pratik R. Sampat <pratikrajesh.sampat@amd.com>
2024-05-29lscpu: New Arm Cortex part numbersJeremy Linton1-0/+2
Arm has announced the Cortex-X925 and published the TRM here: https://developer.arm.com/documentation/102807/0001/?lang=en As well as the Cortex-A725 with a TRM here: https://developer.arm.com/documentation/107652/0001/?lang=en Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
2024-05-21Add Qualcomm Oryon ARM coreSophon1-0/+1
Adding core information for Oryon found in Qualcomm Snapdragon X series SoCs
2024-02-26Adding Neoverse-V3/-N3 ARM coresThomas Kaiser1-0/+2
2024-02-19Add Microsoft as vendor and Cobalt 100 coreThomas Kaiser1-0/+6
https://lore.kernel.org/linux-arm-kernel/b99a7196-011e-4f08-83ec-e63a690ab919@linux.microsoft.com/T/
2023-12-11sys-utils: cleanup license lines, add SPDXKarel Zak1-11/+2
Signed-off-by: Karel Zak <kzak@redhat.com>
2023-11-29Add Phytium FTC310 & FTC664 supportzuoqian1-0/+2
Signed-off-by: zuoqian <zuoqian2023@gmail.com>
2023-09-12Add Phytium FTC862 cpu model.unknown1-0/+1
fix:#2486
2023-09-08Revise/add HiSilicon core namesThomas Kaiser1-1/+3
2023-08-01lscpu: Even more Arm part numbers (early 2023)Jeremy Linton1-0/+6
There have been further MIDR/part numbers published on https://developer.arm.com, they include: Cortex-X4, Cortex-A520, Cortex-A720, Cortex-M85, Cortex-M55 and Cortex-R52+. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
2023-05-29Fix Blizzard-M2-MaxThomasKaiser1-1/+1
2023-05-29Add recent Apple ARM coresThomasKaiser1-0/+6
2023-01-31Adding older Apple cores based on XNU kernel sourceThomasKaiser1-0/+18
Naming based on https://opensource.apple.com/source/xnu/xnu-7195.81.3/osfmk/arm/cpuid.h.auto.html and https://en.wikipedia.org/wiki/List_of_Apple_codenames#Apple-designed_processors No idea about IDs of the new and more interesting Sawtooth and Everest cores in the A16 SoC. I'll leave this for the Asahi people to discover...
2023-01-23Change ThunderX3T110 core name to ThunderX3-T110ThomasKaiser1-1/+1
(for consistency reasons)
2023-01-22Add missing Exynos M5 coreThomasKaiser1-0/+1
https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/uarch.c#L310
2023-01-22Add missing Cavium coresThomasKaiser1-0/+8
https://github.com/ThomasKaiser/sbc-bench/commit/37332238c0a8b7c1555dca9d18a7c98362564416#diff-fdfd2a032c64d6e9ba92a3197cad6b26573c7094433d74efa4ae80f44f65aa99
2023-01-22Add missing Ampere coresThomasKaiser1-1/+7
https://github.com/ThomasKaiser/sbc-bench/commit/37332238c0a8b7c1555dca9d18a7c98362564416#diff-fdfd2a032c64d6e9ba92a3197cad6b26573c7094433d74efa4ae80f44f65aa99
2023-01-22Add missing ARM-coresThomasKaiser1-0/+2
https://github.com/ThomasKaiser/sbc-bench/commit/37332238c0a8b7c1555dca9d18a7c98362564416#diff-fdfd2a032c64d6e9ba92a3197cad6b26573c7094433d74efa4ae80f44f65aa99
2023-01-22Add HiSilicon's 0x48/0xd40 Cortex-A76 variant.ThomasKaiser1-0/+1
Both Kirin 980 and Kirin 810 feature big cores with 0x48/0xd40 ID though they are marketed/documented as Cortex-A76 by HiSilicon themselves. Kirin 980 shows a r1p0 stepping while newer 810 has r3p0. * https://github.com/deater/test_proc/blob/master/arm64/arm64.v8.0x41.0xd05.0x48.0xd40.huawei_mate_20#L37-L71 * https://github.com/termux/proot/issues/190#issuecomment-927013509
2023-01-21Add exynos-m4ThomasKaiser1-0/+1
https://github.com/ThomasKaiser/sbc-bench/blob/master/results/Exynos-9820.cpuinfo
2023-01-21Add 53/002:Samsung Exynos-m3ThomasKaiser1-0/+1
ID 002 for the Exynos-m3 core seems weird since Exynos-m1 had 001 but Samsung's Mongoose line differs only by stepping between M1 and M2 * Mongoose 1, for example [Exynos 8890](https://github.com/ThomasKaiser/sbc-bench/blob/master/results/Exynos-8890-highperformance.cpuinfo): Exynos-m1 / r1p1 * Mongoose 2, for example [Exynos 8895](https://github.com/ThomasKaiser/sbc-bench/blob/master/results/Exynos-8895.cpuinfo): Exynos-m1 / r4p0 * Mongoose 3, for example [Exynos 9810](https://github.com/ThomasKaiser/sbc-bench/blob/master/results/Exynos-9810.cpuinfo): Exynos-m3 / r1p0
2022-09-30lscpu: Add Kryo 3XX Gold coreThomasKaiser1-0/+1
[kzak@redhat.com: - update patch to use '-' between words in CPU name] Signed-off-by: Karel Zak <kzak@redhat.com>
2022-09-02lscpu: Even more Arm part numbersJeremy Linton1-0/+3
Arm has published further MIDR/part numbers on https://developer.arm.com/ip-products/processors/cortex-a. Some of the new ones have already been merged, so lets fill in the gaps with A34, A65AE and X1C. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
2022-07-18Remove closing braces in Apple cores namesThomasKaiser1-8/+8
2022-07-18lscpu: (arm) don't use space in namesKarel Zak1-24/+24
It's seems better to be consistent and use the same convention for all the names. Signed-off-by: Karel Zak <kzak@redhat.com>
2022-07-14lscpu: add missing Apple partsJames Calligeros1-0/+4
Signed-off-by: James Calligeros <jcalligeros99@gmail.com>
2022-07-09lscpu: make Apple part names human-friendlyJames Calligeros1-8/+8
The internal Apple model numbers for the SoCs are somewhat confusing given that they are mostly similar and differ by only one or two digits. Instead, use the public nomenclature for these chips to avoid ambiguity and beautify the output. Signed-off-by: James Calligeros <jcalligeros99@gmail.com>
2022-07-01Fix formatting.Thomas Kaiser1-1/+1
2022-07-01Adding Apple core names, distinguish by SoC/SiP nameThomasKaiser1-3/+9
2022-06-30Add Makalu/Makalu-ELP (A715/X3)ThomasKaiser1-2/+4
Also fix names of A510/A710 cores
2022-05-04lscpu: Add Snapdragon partsJeremy Linton1-0/+3
QC updated the kernel cputype.h to include the Kyro 4xx and 3xx Silver part numbers's. Lets sync that commit and naming. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
2021-12-17lscpu: add additional arm cpu part numbersAli Saidi1-0/+6
Add additional cpu part numbers I can find publicaly available Signed-off-by: Ali Saidi <alisaidi@amazon.com>
2021-11-30lscpu: (arm) remove extra whitespaceKarel Zak1-1/+1
Signed-off-by: Karel Zak <kzak@redhat.com>
2021-11-30Add Earlier Phytium corespanchenbo1-0/+2
2021-11-28Add Apple cores, fix Phytium core namesThomasKaiser1-3/+9
See https://www.spinics.net/lists/arm-kernel/msg879381.html and https://en.wikipedia.org/wiki/FeiTeng_(processor)#Future_processors (S2500 and D2000 are SoCs and contain 4 or 8 FTC663 cores).
2021-08-17fix error ft_part 0x662panchenbo1-1/+1
2021-08-11lscpu:Add Phytium FT-2000+ & S2500 supportpanchenbo1-0/+2
2021-08-11lscpu:Add Phytium aarch64 cpupartpanchenbo1-0/+5
2021-07-02lscpu: don't use DMI if executed with --sysrootKarel Zak1-3/+5
Signed-off-by: Karel Zak <kzak@redhat.com>
2021-06-30lscpu: remove the old codeHuang Shijie1-45/+1
The file "/sys/firmware/dmi/tables/DMI" always exists. The dmi_decode_cputype() can provide more information then arm_smbios_decode(). So remove it to tidy the code. Before this patch, we can get the output from Centos 7.9 who has "/sys/firmware/dmi/entries/4-0/raw" and "/sys/firmware/dmi/tables/DMI": ---------------------------------------------------- BIOS Vendor ID: Ampere(TM) Model name： Neoverse-N1 BIOS Model name: Ampere(TM) Altra(TM) Processor ---------------------------------------------------- After this patch which uses "/sys/firmware/dmi/tables/DMI", in Centos 7.9, we get: ---------------------------------------------------- BIOS Vendor ID: Ampere(TM) Model name： Neoverse-N1 BIOS Model name: Ampere(TM) Altra(TM) Processor Q00-00 CPU @ 2.8GHz BIOS CPU family: 257 ---------------------------------------------------- Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com>
2021-06-16lscpu: get the processor information by DMIHuang Shijie1-0/+2
The patch :367c85c47286 ("lscpu: use SMBIOS tables on ARM for lscpu") relies on the existence of "/sys/firmware/dmi/entries/4-0/raw", which may not exist in standard linux kernel. But "/sys/firmware/dmi/tables/DMI" should exist and can provide the required processor information. This patch uses "/sys/firmware/dmi/tables/DMI" to get the processor information: Before this patch, in Ampere Altra platform, the lscpu output is: --------------------------------------------- Architecture: aarch64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 160 On-line CPU(s) list: 0-159 Vendor ID: ARM Model name: Neoverse-N1 Model: 1 Thread(s) per core: 1 Core(s) per socket: 80 Socket(s): 2 ........................................ --------------------------------------------- After this patch, we can use get the lscpu output in Ampere Altra platform: --------------------------------------------- Architecture: aarch64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 160 On-line CPU(s) list: 0-159 Vendor ID: ARM BIOS Vendor ID: Ampere(R) Model name: Neoverse-N1 BIOS Model name: Ampere(R) Altra(R) Processor Q00-00 CPU @ 3.0GHz Model: 1 Thread(s) per core: 1 Core(s) per socket: 80 Socket(s): 2 ........................................ --------------------------------------------- [kzak@redhat.com: - s/sprintf/snprintf/] Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com> Signed-off-by: Karel Zak <kzak@redhat.com>
2021-05-31lscpu: fix NVIDIA ARM hw implementer spelling caseVille Skyttä1-1/+1
Ref respective vendor sites. Signed-off-by: Ville Skyttä <ville.skytta@iki.fi> Signed-off-by: Karel Zak <kzak@redhat.com>
2021-05-31lscpu: recognize more ARM implementersVille Skyttä1-0/+4
Add just the implementer string, no parts yet. Refs https://developer.arm.com/documentation/ddi0595/2021-03/AArch64-Registers/MIDR-EL1--Main-ID-Register Refs https://github.com/torvalds/linux/blob/b90e90f40b4ff23c753126008bf4713a42353af6/arch/arm64/include/asm/cputype.h#L54 Signed-off-by: Ville Skyttä <ville.skytta@iki.fi>
2020-12-15lscpu: remove unnecessary prefix from static functionKarel Zak1-2/+2
Signed-off-by: Karel Zak <kzak@redhat.com>
2020-11-20lscpu: show the number of physical socket on aarch64 machine without ACPI PPTTMasayoshi Mizuma1-0/+2
Show the number of the number of physical socket even if the sysfs doesn't have the physical socket information. Note, lscpu shows the number of physical socket as 'Socket(s):' only if root user runs it because accessing the DMI table requires root privilege. Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
2020-11-20lscpu: use cluster on aarch64 machine which doesn't have ACPI PPTTMasayoshi Mizuma1-0/+13
lscpu may show the wrong number of sockets if the machine is aarch64 and doesn't have ACPI PPTT. That's because lscpu shows the number of sockets by using a sysfs entry (cpu/cpuX/topology/core_siblings). The sysfs entry is set by MPIDR_EL1 register if the machine doesn't have ACPI PPTT. MPIDR_EL1 doesn't show the physical socket information directly. It shows the affinity level. According to linux/arch/arm64/kernel/topology.c:store_cpu_topology(), the top level of affinity is called as 'Cluster'. Use Cluster instead of Socket on the machine which doesn't have ACPI PPTT. This patch is useful for aarch64 machine which is based on ARM SBBR v1.0 and v1.1, the specs don't require ACPI PPTT. ARM SBBR v1.2 requires ACPI PPTT. Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
2020-11-13lscpu-arm: Add "BIOS Vendor ID" and "BIOS Model name" to show the SMBIOS ↵Masayoshi Mizuma1-12/+7
information. After commit: 367c85c47 ("lscpu: use SMBIOS tables on ARM for lscpu"), Model name for A64FX shows like as: Model name: 461F0010 That's because 367c85c47 changes to get the modelname from Processor Version of SMBIOS. To fix that, use the hard corded table to show the "Model name" and add two new lines; "BIOS Vendor ID" and "BIOS Model name" to show the SMBIOS information. lscpu shows the SMBIOS information when root user runs it because accessing the SMBIOS information requires root privilege. [kzak@redhat.com: - port the patch to new lscpu code] Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com> Signed-off-by: Karel Zak <kzak@redhat.com>
2020-11-13lscpu: Even more Arm part numbersJeremy Linton1-0/+6
Over the past two years Arm has published further MIDR/part numbers on https://developer.arm.com/ip-products/processors/cortex-a. Lets sync the arm_part structure for A65, A76AE, A77 and A78*. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
2020-11-13lscpu: (arm) reuse parsed vendor IDKarel Zak1-1/+8
Signed-off-by: Karel Zak <kzak@redhat.com>
2020-11-13lscpu: merge new API to lscpu.hKarel Zak1-1/+1
Signed-off-by: Karel Zak <kzak@redhat.com>
2020-11-13lscpu: convert ARM decoding to new APIKarel Zak1-64/+96
Signed-off-by: Karel Zak <kzak@redhat.com>
2020-09-30lscpu: don't use smbios when read snapshotsKarel Zak1-2/+3
Signed-off-by: Karel Zak <kzak@redhat.com>
2020-09-29lscpu: use SMBIOS tables on ARM for lscpuJeffrey Bastian1-29/+91
ARM SBBR (Sever Base Boot Requirements) require SMBIOS tables, and SMBIOS Type 4 describes the CPU manufacturer and model name (among other details). If SMBIOS Type 4 is present, use it to extract these strings. Example output (before and after the patch) on an HP m400, Lenovo HR330A, and HPE Apollo 70: [root@hp-m400 ~]# /usr/bin/lscpu | grep -i -e vendor -e model -e stepping Vendor ID: APM Model: 1 Model name: X-Gene Stepping: 0x0 [root@hp-m400 ~]# ./lscpu | grep -i -e vendor -e model -e stepping Vendor ID: AppliedMicro Model: 1 Model name: X-Gene Stepping: 0x0 [root@lenovo-hr330a ~]# /usr/bin/lscpu | grep -i -e vendor -e model -e stepping Vendor ID: APM Model: 2 Model name: X-Gene Stepping: 0x3 [root@lenovo-hr330a ~]# ./lscpu | grep -i -e vendor -e model -e stepping Vendor ID: Ampere(TM) Model: 2 Model name: eMAG Stepping: 0x3 [root@hpe-apollo-70 ~]# /usr/bin/lscpu | grep -i -e vendor -e model -e stepping Vendor ID: Cavium Model: 1 Model name: ThunderX2 99xx Stepping: 0x1 [root@hpe-apollo-70 ~]# ./lscpu | grep -i -e vendor -e model -e stepping Vendor ID: Cavium Inc. Model: 1 Model name: Cavium ThunderX2(R) CPU CN9980 v2.1 @ 2.20GHz Stepping: 0x1 [kzak@redhat.com: - move dmi_header to lscpu.h - make arm_cpu_smbios() more robust for failed open() and read() - use original arm_cpu_decode() also on failed arm_cpu_smbios()] Signed-off-by: Jeffrey Bastian <jbastian@redhat.com> Signed-off-by: Karel Zak <kzak@redhat.com>
2020-09-29lscpu: Add FUJITSU aarch64 A64FX cpupartShunsuke Nakamura1-0/+6
Add an entry for FUJITSU aarch64 part A64FX. I tested it on the FX1000. Signed-off-by: Shunsuke Nakamura <nakamura.shun@fujitsu.com>
2020-09-11add Carmel from NVIDIATomoaki Teshima1-0/+1
2020-04-20[clang-tidy] fix wrong *cmp usageRosen Penev1-1/+1
Found with bugprone-suspicious-string-compare Signed-off-by: Rosen Penev <rosenp@gmail.com>
2020-03-04lscpu: use official name for HiSilicon tsv110Karel Zak1-2/+2
Addresses: https://github.com/karelzak/util-linux/issues/969 Signed-off-by: Karel Zak <kzak@redhat.com>
2019-10-11lscpu: Add HiSilicon aarch64 tsv110 cpupartJohn Garry1-0/+6
Add an entry for the HiSilicon aarch64 part tsv110. Another known alias for this part is TaishanV110, and it can be found in the Kunpeng920/Hi1620 SoC. Signed-off-by: John Garry <john.garry@huawei.com>
2019-05-16lscpu: Add additional aarch64 modelsJeremy Linton1-0/+3
ARM has released docs for Cortex-A76, Neoverse-N1 and Neoverse-E1. That means we know the midr partnums, so we can add them to the human readable model name table. Signed-off-by: Jeremy Linton <lintonrjeremy@gmail.com>
2018-08-13lscpu: fixed part ID for ARM Cortex-M7Mark Sheppard1-1/+1
2018-04-12lscpu: Cortex-A12 merged into Cortex-A17Karel Zak1-1/+1
References: https://community.arm.com/processors/b/blog/posts/arm-cortex-a17-cortex-a12-processor-update Signed-off-by: Karel Zak <kzak@redhat.com>
2018-02-13lscpu-arm: add Faraday And Brahma coresRiku Voipio1-1/+8
Add a handful of more rare cores. Broadcom Brahma cores are used in Access Points and Faraday was used on some Network Storage Devices. Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
2018-01-22lscpu: (arm) cleanup codeKarel Zak1-19/+37
* check for strtol() errors * fix indention * fix coding style Signed-off-by: Karel Zak <kzak@redhat.com>
2018-01-22lscpu: move ARM decoding to lscpu-arm.cKarel Zak1-0/+227
Signed-off-by: Karel Zak <kzak@redhat.com>
generated by cgit 1.2.3-korg (git 2.43.0) at 2025-12-03 18:02:04 +0000